Non-Overlapping Gate Drive Circuit With Replica Delay Tracking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing gate drive circuitry for power stages in integrated circuits faces challenges in efficiently managing voltage level shifts and ensuring break-before-make operations across varying process, voltage, and temperature conditions, particularly due to the large area consumption of high voltage protection devices in level shifters.
Innovation Solution
A power stage design incorporating a second gate drive circuit with multiple buffers and electronic devices that apply a delay to track the delay of the first gate drive circuit, ensuring that the NMOS transistor is turned on after the PMOS transistor has turned off and vice versa, while efficiently managing high voltage levels through PVT-tracking circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage protection devices are used in level shifters to ensure reliable operation, then reliability is improved, but area consumption increases
Solution Approach 1:
The patent uses a replica delay circuit that copies the delay characteristics of the first gate drive circuit. This replica circuit allows the system to track and match delays without requiring large high voltage protection devices, thereby reducing area while maintaining reliable break-before-make operation
Solution Approach 2:
The patent changes the approach from using fixed high voltage protection devices to dynamically adjusting delay parameters through a replica circuit. By matching delay parameters between the first gate drive circuit and the second gate drive circuit, the system achieves reliable operation with reduced area consumption
2Reliability
If delay tracking circuitry is added to ensure break-before-make operation, then reliability is improved, but device complexity increases
Solution Approach 1:
The replica delay circuit serves multiple functions: it tracks the delay of the first gate drive circuit, generates the appropriate delay for the second gate drive circuit, and ensures break-before-make operation. This multi-functionality reduces overall system complexity compared to using separate dedicated circuits for each function
Solution Approach 2:
The patent implements a feedback mechanism where the replica delay circuit continuously monitors and matches the delay characteristics of the first gate drive circuit. This feedback approach ensures reliable break-before-make operation while using a relatively simple circuit configuration
Data Source
AI summary
Certain aspects of the present disclosure generally relate to a power stage. The power stage generally includes a first transistor, a second transistor having a drain coupled to a drain of the first transistor, a first gate drive circuit coupled between an input node of the power stage and a gate of the first transistor, and a second gate drive circuit having a first signal path coupled between the input node and a gate of the second transistor. In certain aspects, the second gate drive circuit comprises a plurality of buffers in the first signal path, and a plurality of electronic devices coupled to the plurality of buffers and configured to apply a delay associated with driving the gate of the second transistor to track a delay associated with driving the gate of the first transistor via the first gate drive circuit.