Non-Planar CMOS Gate Stack for Multi-Threshold Voltage Tuning
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Solution Overview
Problem
Existing multi-threshold voltage CMOS devices face challenges in modifying threshold voltages of non-planar transistor devices, such as vertical fin and nanosheet transistors, to achieve desired electrical characteristics without compromising device performance.
Innovation Solution
The introduction of a dipole layer formed by transforming aluminum-containing conversion layer segments into the gate dielectric layer, which shifts the threshold voltages of n-type and p-type field effect transistors, allowing for distinct threshold voltage settings in neighboring regions on a substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a dipole layer is introduced to adjust threshold voltage, then threshold voltage control is improved, but device structure complexity increases
Solution Approach 1:
The dipole layer is nested within the gate dielectric layer structure, specifically positioned between the interfacial layer and the gate electrode. This nesting approach allows the dipole layer to be integrated into the existing gate stack without requiring separate processing steps or additional structural complexity outside the gate region.
Solution Approach 2:
The dipole layer acts as an intermediary element between the interfacial layer and the gate electrode, modifying the electric field distribution and threshold voltage without requiring direct modification of the channel or source/drain structures. This intermediary approach enables threshold voltage control while maintaining the integrity of other device components.
2Manufacturing precision
If different work function layers are used for n-type and p-type FETs, then threshold voltage differentiation is improved, but manufacturing process complexity increases
Solution Approach 1:
Different work function materials are applied to different regions of the gate structure - specifically, one work function material for n-type FET gates and another for p-type FET gates. This local differentiation allows each transistor type to have optimized threshold voltage characteristics while using a unified gate structure design.
Solution Approach 2:
The gate structure is segmented into different regions corresponding to n-type and p-type FETs, with each segment receiving a specific work function material treatment. This segmentation enables independent optimization of threshold voltages for each transistor type without affecting the other.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of non-planar transistor devices with adjusted threshold voltages, improving the electrical performance and flexibility of CMOS devices by creating distinct threshold voltages for n-type and p-type transistors, enhancing their operational efficiency.
Implementation Method 1
a dipole layer on the interfacial layer... such that the first field effect transistor device and second field effect transistor device each have a different threshold voltage than a first field effect transistor device and second field effect transistor device without a dipole layer
Data Source
AI summary
A device is provided. The device includes an interfacial layer on a semiconductor device channel. The device further includes a dipole layer on the interfacial layer, and a gate dielectric layer on the dipole layer. The device further includes a first work function layer associated with a first field effect transistor device; and a second work function layer associated with a second field effect transistor device, such that the first field effect transistor device and second field effect transistor device each have a different threshold voltage than a first field effect transistor device and second field effect transistor device without a dipole layer.