Non-planar Gate Thin Film Transistor Sidewall Channel
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Solution Overview
Problem
Conventional thin-film transistors face limitations in drive current and performance due to their planar structure, which restricts their density and efficiency in integrated circuits, particularly in applications requiring high packing density.
Innovation Solution
The development of a non-planar gate thin film transistor with a semiconductive layer formed on the sidewall of a substrate, featuring a gate dielectric layer and a gate in contact with it, allowing for increased effective width and improved current flow through a circular cross-section, enhancing both drive current and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If transistor width is increased to address limited drive current, then drive current is improved, but layout area increases which is not acceptable for high density packing
Solution Approach 1:
The patent transitions from a planar transistor structure to a three-dimensional structure where the semiconductive layer is formed on the sidewall of the gate structure. This vertical configuration allows the effective channel width to extend in the vertical dimension while maintaining a compact lateral footprint, thereby increasing drive current without proportionally increasing layout area
Solution Approach 2:
The semiconductive layer is nested within the three-dimensional structure formed by the gate electrode and gate dielectric layer. The gate electrode surrounds the semiconductive layer in a wrap-around configuration, creating a nested arrangement that maximizes the effective channel width within a compact lateral space, improving current drive capability without increasing layout area
2Ease of manufacture
If planar TFT structure is used, then manufacturing is simple, but performance and drive current are limited
Solution Approach 1:
The transistor structure is segmented into distinct functional layers: gate dielectric layer, gate electrode, and semiconductive layer formed on the sidewall. This segmentation allows each component to be optimized independently while maintaining a systematic manufacturing process that builds complexity through sequential layer formation
Solution Approach 2:
The invention moves from two-dimensional planar geometry to three-dimensional structure with the semiconductive layer formed on the sidewall of the gate structure. This dimensional transition enables enhanced drive current through increased effective channel width while using manufacturing techniques that extend conventional thin-film deposition and patterning processes into the vertical dimension
Data Source
AI summary
Embodiments of the present disclosure describe a non-planar gate thin film transistor. An integrated circuit may include a plurality of layers formed on a substrate, and the plurality of layers may include a first one of a source or drain, an inter-layer dielectric (ILD) formed on the first one of the source or drain, and a second one of the source or drain formed on the ILD. A semiconductive layer may be formed on a sidewall of the plurality of layers. A gate dielectric layer formed on the semiconductive layer, and a gate may be in contact with the gate dielectric layer.