Nonplanar III-N Transistors with Compositionally Graded Channels
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Solution Overview
Problem
Conventional mobile computing platforms face limitations in scaling to smaller and more power-efficient form factors due to the use of incompatible transistor technologies for power management ICs (PMIC) and radio frequency ICs (RFIC), which hinder the integration of these components into a single System on Chip (SoC) solution, lacking a scalable transistor technology with both high gain cutoff frequency and high breakdown voltage.
Innovation Solution
The development of non-planar III-N transistors with a compositionally graded semiconductor channel that forms a 3-dimensional electron gas, enabling reduced extrinsic resistance, higher drain breakdown voltages, and integration with CMOS technologies to create a monolithic SoC solution for mobile computing platforms, incorporating high voltage and high power circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If conventional silicon MOS technology is used in PMIC, then voltage conversion and power distribution can be managed, but breakdown voltage is limited and source-to-drain separation must be large
Solution Approach 1:
The patent changes the material parameter from silicon to group III-nitride semiconductors, which inherently provides higher breakdown voltage capability. This material substitution enables high voltage operation without requiring proportionally large device dimensions, resolving the contradiction between strength and length.
2Adaptability or versatility
If GaAs HBT technology is used in RFIC, then power amplification at high frequency can be achieved, but the technology is incompatible with silicon PMIC and CMOS logic
Solution Approach 1:
The patent employs group III-nitride heterostructure field effect transistors that can universally serve multiple functions: high voltage switching in PMIC, high frequency power amplification in RFIC, and logic control functions. This single transistor technology replaces the need for three different technologies (silicon MOS, GaAs HBT, and CMOS), reducing device complexity and enabling monolithic integration.
3Strength
If III-N transistors use 2D electron gas at abrupt hetero-interface, then high breakdown voltage and gain cutoff frequency can be obtained, but the footprint is large and multi-gate architecture is difficult to implement
Solution Approach 1:
The patent transitions from planar 2D electron gas channels to vertically extended 3D electron gas channels through compositionally graded III-nitride semiconductor structures. This dimensional change enables multi-gate architectures (such as tri-gate or gate-all-around configurations) that provide enhanced control and reduced footprint while maintaining high breakdown voltage and frequency performance.
Solution Approach 2:
The patent uses compositionally graded III-nitride semiconductor materials (e.g., AlGaN-InGaN-GaN superlattices) that form 3D electron gas channels. These composite material structures enable vertical channel formation with enhanced carrier confinement and mobility, allowing compact multi-gate device geometries while preserving the high voltage and frequency characteristics of III-N devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the integration of PMIC and RFIC functions within a single SoC, achieving high power added efficiencies, reduced substrate surface area, and improved scalability, enabling high-frequency operation suitable for broadband wireless data transmission while maintaining low power consumption.
Implementation Method 1
a 3-dimensional electron gas (3 DEG) within the III-N semiconductor channel... This 2D sheet charge is formed at the abrupt hetero-interface formed by epitaxial deposition of a film with larger spontaneous and piezoelectric polarization
Implementation Method 2
enabling reduced extrinsic resistance... nonplanar III-N transistors with compositionally graded semiconductor channels
Implementation Method 3
higher drain breakdown voltages... compositionally graded III-N semiconductor channel... graded III-N semiconductor channel layer
Data Source
AI summary
A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least both sidewall surfaces in response to a gate bias voltage. In embodiments, a gate stack is deposited completely around a nanowire including a III-N semiconductor channel compositionally graded to enable formation of a transport channel in the III-N semiconductor channel adjacent to both the polarization layer and the transition layer in response to a gate bias voltage.