Non-Planar Transistor Isolation for Uniform Gate Height
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Solution Overview
Problem
The varying densities of semiconductor channels in non-planar transistors lead to inconsistent heights of STI structures, affecting the performance of transistors due to differing gate heights formed over these structures.
Innovation Solution
A method is employed to form a thick enough cured insulation layer stack between channels of varying densities, allowing a uniform etching process to achieve similar heights of exposed channels, thereby ensuring consistent gate heights for active gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If channels are arranged with varying densities to increase integration, then integration density is improved, but STI structure height consistency deteriorates
Solution Approach 1:
The patent divides the semiconductor substrate into multiple regions with different channel densities. Each region is independently processed to achieve uniform STI heights within that region, then all regions are combined. This segmentation allows high integration density overall while maintaining manufacturing precision within each segment.
Solution Approach 2:
The patent applies different processing conditions to different regions based on their local channel density characteristics. Regions with higher channel density receive different etching or deposition parameters compared to lower density regions, ensuring that each local area achieves the target STI height consistency appropriate for its density level.
2Adaptability or versatility
If gate structures are formed over channels of varying densities, then device functionality is improved, but gate height uniformity deteriorates
Solution Approach 1:
The patent performs preliminary formation of STI structures with region-specific height adjustments before forming the gate structures. This preliminary action ensures that when gates are formed across all regions, they rest on STI structures that have been pre-adjusted to compensate for underlying channel density variations, resulting in uniform gate heights despite varying channel densities.
Solution Approach 2:
The patent changes processing parameters (such as etch depth, deposition thickness, or removal amount) based on the regional channel density. By adjusting these parameters across different regions, the final gate height is uniform even though the underlying channel densities vary, allowing both functionality and precision to be achieved.
Data Source
AI summary
A semiconductor device in a first area includes first non-planar semiconductor structures separated with a first distance, and a first isolation region including a first layer and a second layer that collectively embed a lower portion of each of the first non-planar semiconductor structures. At least one of the first layer or second layer of the first isolation region is in a cured state. The semiconductor device in a second area includes second non-planar semiconductor structures separated with a second distance, and a second isolation region including a first layer and a second layer that collectively embed a lower portion of each of the second non-planar semiconductor structures. At least one of the first or second layer of the second isolation region is in a cured state.