Non-Planar MIM Interconnect Structure for Backside Power Delivery
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Solution Overview
Problem
As critical dimensions decrease in integrated circuit manufacturing, existing interconnection schemes face challenges in optimizing material usage and process flows to construct high-performance structures, leading to increased resistance and power loss in on-chip interconnects, and competition for resources between power and signal networks.
Innovation Solution
Implementing a back-side power delivery architecture using metal-insulator-metal (MIM) capacitors on the wafer, which separates power and signal networks, allowing for larger, less resistant power rails and unique electrical connections, and incorporating a non-planar MIM capacitor structure to reduce power supply noise and increase decoupling capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If critical dimensions are decreased to increase transistor density, then more transistors can be manufactured on a single wafer, but resistance and power loss in on-chip interconnects increase
Solution Approach 1:
The patent introduces a non-planar, three-dimensional interconnect structure that extends vertically above the substrate surface. By adding this vertical dimension to the traditionally planar interconnect layout, the invention achieves longer power delivery paths without increasing lateral footprint, thereby reducing resistance and power loss while maintaining high transistor density
2Ease of manufacture
If traditional planar interconnect structures are used, then manufacturing is simpler, but power delivery efficiency is insufficient and noise spikes increase
Solution Approach 1:
The patent employs curved and non-planar interconnect paths that follow the surface topology created by recessed regions. These curved paths allow the interconnects to navigate around obstacles and utilize vertical space efficiently, improving power delivery efficiency and reducing noise without significantly complicating the manufacturing process
Solution Approach 2:
The invention nests interconnect structures within recessed regions of the substrate surface. By placing conductive paths inside these recesses and extending them vertically, the design achieves enhanced power delivery efficiency and reduced electromagnetic interference while maintaining compatibility with standard fabrication processes
3Device complexity
If power and signal networks share the same interconnect layer, then device complexity is reduced, but electromagnetic interference and noise spikes increase
Solution Approach 1:
The patent segments the interconnect system into distinct functional regions: recessed regions containing power delivery interconnects and elevated regions containing signal interconnects. This spatial segmentation physically separates power and signal networks, reducing electromagnetic interference and noise spikes while maintaining relatively simple overall device structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances power delivery efficiency, reduces power loss, and improves reliability by minimizing noise spikes and electromagnetic failures, while allowing for flexible design without compromising signal integrity.
Implementation Method 1
non-planar MIM capacitor structure to reduce power supply noise and increase decoupling capacitance
Implementation Method 2
applying a high-k dielectric layer in between the plurality of first electrodes in the subtractive-etched interconnect wiring level and the another plurality of second electrodes in the damascene interconnect wiring level
Data Source
AI summary
A semiconductor device including an interleaved/nested structure of subtractive interconnects and damascene interconnects. The semiconductor device includes a subtractive-etched interconnect wiring level having subtractive interconnects and a damascene interconnect wiring level having damascene interconnects. The subtractive-etched interconnect wiring level includes first electrodes that have a first potential second electrodes that have a second potential different from the first potential, with the second electrodes generated to interleave the first electrodes. The semiconductor also includes a damascene interconnect wiring level that includes other first electrodes having the first potential, and other second electrodes having the second potential. In the damascene interconnect wiring level, the other second electrodes are also interleaved by the other first electrodes.