Non-Planar Passivation and Polyimide Layers for 3D Die Adhesion
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Solution Overview
Problem
Existing 3D IC devices face issues with wafer bow and die-level warpage, as well as decreased adhesion between stacked dies, leading to micro-cracks and delamination, particularly with thinner wafers and increased die stacking.
Innovation Solution
A die structure for 3D IC devices featuring a non-planar passivation layer with projections and a polyimide layer with varying heights, designed to modulate wafer bow and improve die adhesion through increased surface area, using photolithography and etching processes to shape the layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the wafer thickness is reduced to increase die stacking density, then the productivity and integration density are improved, but the wafer bow and die-level warpage increase leading to micro-cracks and delamination
Solution Approach 1:
The passivation layer is engineered with spatially varying thickness, featuring protrusions in central regions and recesses at peripheral regions. This non-uniform thickness distribution creates localized mechanical properties that compensate for stress variations across the die surface, preventing warpage-induced delamination while maintaining thin-wafer high-density stacking
Solution Approach 2:
The patent modifies the physical parameters of the passivation layer by controlling its thickness profile through photolithography and etching processes. The thickness varies from thicker central regions to thinner peripheral regions, changing the mechanical stress distribution parameters to counteract wafer bow and maintain adhesion in high-density stacked configurations
2Productivity
If the number of stacked dies is increased to improve integration density, then the productivity is improved, but the stress and warpage between layers increase causing delamination
Solution Approach 1:
The passivation layer features localized thickness variations with protrusions positioned in central regions and recesses at peripheries. This creates differentiated mechanical support zones that accommodate inter-layer stress from multiple stacked dies, maintaining adhesion strength across the stack while enabling high integration density
Solution Approach 2:
The solution transitions from a planar (2D) passivation layer to a three-dimensional (3D) non-uniform thickness profile. This vertical dimensionality addition allows the passivation layer to compensate for multi-layer stacking stresses by providing varying mechanical support at different locations, enabling higher die counts without delamination
3Ease of manufacture
If a planar passivation layer is used to simplify manufacturing, then the ease of manufacture is improved, but the wafer bow and die warpage cannot be modulated reducing reliability
Solution Approach 1:
The non-uniform passivation layer thickness profile is formed in advance during the fabrication process using photolithography and etching. This preliminary structuring of the passivation layer pre-compensates for anticipated wafer bow and die warpage, ensuring reliability before die stacking occurs
Solution Approach 2:
The patent modifies the thickness parameter of the passivation layer to create a non-uniform profile. This parameter change enables the passivation layer to actively modulate wafer bow and die warpage while remaining compatible with standard semiconductor fabrication processes
Data Source
AI summary
A die, an integrated circuit (IC) device including two or more stacked dies, and a process of forming a die are provided. The die includes a circuit, a passivation layer arranged above the circuit and includes a top side and a bottom side, and a polyimide layer disposed on the top side of the passivation layer. The top side of the passivation layer includes portions of different respective heights extending vertically away from the circuit. A top side of the polyimide layer opposite the top side of the passivation layer includes portions of different respective heights extending vertically away from the circuit such that the surface area of the top side of the polyimide layer is increased compared to a planar top side.