Non-Planar RDL Trace Structure for Stress-Resistant Packaging
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Solution Overview
Problem
Conventional planar redistribution layers (RDLs) in semiconductor packaging are susceptible to delamination, cracking, and stress damage due to thermal property differences and planar configuration, leading to poor adhesion and increased stress accumulation.
Innovation Solution
A non-planar RDL trace configuration with a hilling topography, featuring peaks and valleys, is formed using a gradient grayscale mask or multi-exposure process, providing increased stress buffering and improved adhesion by conforming to a patterned passivation layer, and increasing the contact area between the RDL trace and passivation layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar RDL configuration is used, then the manufacturing process is simple, but the adhesion is poor and stress accumulation increases
Solution Approach 1:
The patent applies curvature by transforming the planar RDL configuration into a non-planar configuration with peaks and valleys. This curved surface increases the contact area between the RDL and passivation layer, thereby improving adhesion quality while maintaining manufacturing feasibility through conventional deposition processes
2Device complexity
If a planar RDL configuration is used, then the structure is simple, but stress accumulation increases leading to delamination and cracking
Solution Approach 1:
The non-planar configuration with curved surfaces distributes thermal stress more effectively compared to a flat structure. The peaks and valleys create a stress-buffering effect that prevents stress concentration, thereby reducing delamination and cracking while maintaining reasonable structural complexity
Solution Approach 2:
The patent changes the geometric parameters of the RDL from a flat plane to a three-dimensional surface with varying heights (peaks and valleys). This parameter change transforms the stress distribution pattern, allowing the structure to better accommodate thermal expansion differences and improve stress resistance
3Reliability
If a non-planar RDL configuration with peaks and valleys is used, then adhesion and stress buffering are improved, but the manufacturing process complexity increases
Solution Approach 1:
The curved non-planar configuration can be formed using conventional semiconductor manufacturing techniques such as selective etching or deposition on patterned substrates. This approach achieves the adhesion benefits of curvature without requiring entirely new manufacturing processes, thus limiting the increase in process complexity
Data Source
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AI summary
A semiconductor device package includes a semiconductor device and an electrically conductive pad disposed in contact with a surface of the semiconductor device. The semiconductor device package further includes a redistribution layer (RDL) formed over the electrically conductive pad and the surface of the semiconductor device, and an electrical connector disposed over and electrically coupled to the RDL. The RDL includes a first passivation layer disposed over a surface of the semiconductor device and the electrically conductive pad, and further includes an RDL trace. The RDL trace includes a first portion in contact with the electrically conductive pad, a second portion in contact with one of the electrical connector or an underlying metallization layer in contact with the electrical connector, and a third portion having a non-planar and undulating configuration relative to the surface of the semiconductor device.