Non-Planar Semiconductor Layout for FinFET and High-Voltage Integration
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Solution Overview
Problem
Current semiconductor devices face challenges in integrating high-voltage and FinFET devices due to issues such as current leakage and control of breakdown voltage, especially as device scales decrease.
Innovation Solution
A semiconductor device design featuring a substrate with planar and non-planar regions, where bases and fin-shaped structures are formed with different heights, and bumps on the non-planar region have varying heights to improve device balance and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high-voltage devices and FinFET devices are integrated on the same chip, then device functionality and power efficiency are improved, but current leakage and breakdown voltage control become problematic
Solution Approach 1:
The substrate is divided into multiple regions with different heights: a first planar region, a second planar region, and a non-planar region with bumps of varying heights. High-voltage devices are placed on the first planar region while FinFET devices are placed on the second planar region, physically separating the two device types to prevent current leakage between them while maintaining integration on the same chip.
Solution Approach 2:
The invention introduces a vertical dimension by creating bumps of different heights in the non-planar region. The substrate transitions from a traditional two-dimensional planar structure to a three-dimensional structure with varying elevations, allowing different device types to be positioned at different heights and preventing harmful electrical interactions while maintaining compact integration.
2Adaptability or versatility
If high-voltage devices and FinFET devices are integrated on the same chip, then device functionality is improved, but breakdown voltage control becomes difficult
Solution Approach 1:
The substrate is segmented into distinct planar regions and a non-planar region with bumps of controlled heights. This segmentation allows independent optimization of breakdown voltage characteristics for high-voltage devices on the first planar region while maintaining proper electrical isolation and control through the structured transition zones.
Solution Approach 2:
Different regions of the substrate are given different local characteristics: the first planar region is optimized for high-voltage devices with appropriate breakdown voltage control, the non-planar region contains bumps with specific height variations to control electrical fields, and the second planar region is optimized for FinFET devices. Each region's structure is tailored to its specific functional requirements.
3Ease of manufacture
If planar MOS transistors are used, then manufacturing is simpler, but channel control and current capability are limited
Solution Approach 1:
The invention transitions from traditional planar MOS transistors to FinFET structures by introducing vertical fins that extend upward from the substrate. This three-dimensional structure increases the gate-to-channel overlapping area, enabling much better control of the channel region and significantly higher current capability while maintaining compatibility with standard semiconductor manufacturing processes.
Solution Approach 2:
The FinFET structure introduces curved or angled sidewalls in the fin regions, creating a three-dimensional geometry that increases the effective channel width and gate control area compared to flat planar structures. This curvature allows for enhanced electrical control and higher current density without requiring proportionally larger device footprints.
Data Source
AI summary
A semiconductor device includes a substrate having a first planar region, a second planar region adjacent to the first planar region, a non-planar region between the first planar region and the second planar region, a first base on the first planar region, a second base on the second planar region, and a plurality of bumps on the non-planar region. Preferably, the bumps have different heights, top surfaces of the first base and the second base are coplanar, the top surface of the bumps is lower than the top surface of the first base, and the height of the bumps closer to the first planar region is greater than the height of the bumps closer to the non-planar region.