Non-Planar Source Follower Transistors for Image Sensors
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Solution Overview
Problem
As pixel count increases in image sensors, bitline setting time also increases due to higher bitline loading, necessitating higher transconductance in source follower transistors, which can lead to undesirable noise like Random Telegraph Signal (RTS) when channel length is shortened or pixel size is enlarged.
Innovation Solution
The implementation of source follower transistors with a non-planar structure that provides a large effective channel width, achieved through semiconductor substrate trench structures and isolation layer configurations, allowing for increased transconductance without physical width expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the source follower channel length is shortened to increase transconductance, then the operating speed is improved, but RTS noise increases
Solution Approach 1:
The patent transitions from a conventional planar channel structure to a three-dimensional FinFET structure. The channel is formed as a vertical fin extending from the substrate surface, creating a non-planar geometry that increases the effective channel width without increasing the lateral footprint. This dimensional change allows simultaneous achievement of high transconductance (for speed) and adequate channel length (to suppress RTS noise).
Solution Approach 2:
The channel width is segmented into multiple fins or ridges that extend vertically from the substrate. Each fin acts as an independent conduction path, and the total effective channel width is the sum of all fin widths. This segmentation allows the channel to achieve large effective width for high transconductance while maintaining sufficient length in each fin to reduce RTS noise, resolving the contradiction between speed and noise.
2Speed
If the source follower channel width is increased to increase transconductance, then the operating speed is improved, but the pixel size increases
Solution Approach 1:
The patent utilizes the vertical dimension by creating FinFET structures that extend upward from the substrate surface. The effective channel width includes contributions from the vertical fin surfaces, allowing the transistor to achieve large channel width for high transconductance without increasing the lateral pixel area. This enables high-speed operation within compact pixel dimensions.
Solution Approach 2:
The channel structure is nested vertically within the pixel area. Multiple fin structures are formed in vertical stacks or adjacent vertical configurations, effectively nesting conduction paths within the available lateral space. This nesting approach maximizes the effective channel width within the constrained pixel footprint, achieving high operating speed without pixel size expansion.
Data Source
AI summary
Image sensors include a photodiode disposed in a semiconductor substrate and a transistor operatively coupled to the photodiode. At least three substrate trench structures are formed in the semiconductor substrate, defining two nonplanar structures, each having a plurality of sidewall portions. An isolation layer includes at least three isolation layer trench structures, each being disposed in a respective one of the three substrate trench structures. A gate includes three fingers, each being disposed in a respective one of the three isolation layer trench structures. An electron channel of the transistor extends along the plurality of sidewall portions of the two nonplanar structures in a channel width plane.