Non-Planar I/O and Logic Transistors With Split Gate Workfunctions
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Solution Overview
Problem
Conventional semiconductor manufacturing processes face challenges in scaling multi-gate transistors, particularly in achieving independent performance control of I/O and logic transistors on common substrates due to the limitations of shared workfunctions and substrate implant differentiation.
Innovation Solution
The approach involves using a carbon hardmask to selectively etch and pattern different workfunction metal layers for I/O and logic transistors, allowing for independent control of gate workfunctions without additional mask operations, enabling distinct performance characteristics for each device type.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional processes use shared workfunctions on common substrates, then manufacturing simplicity is maintained, but independent performance control of I/O and logic transistors is lost
Solution Approach 1:
The patent applies local quality by depositing different workfunction metal layers (e.g., tungsten for I/O transistors, titanium nitride for logic transistors) in specific regions of the substrate. This allows each transistor type to have locally optimized workfunction values tailored to their performance requirements, while maintaining a unified manufacturing process flow on common substrates.
Solution Approach 2:
The manufacturing process is segmented into region-specific deposition steps where different workfunction metal layers are selectively formed over different transistor regions. This segmentation enables independent performance control without requiring separate substrate processing, effectively dividing the uniform substrate into functionally distinct zones.
2Adaptability or versatility
If substrate implant differentiation is used to control performance, then device performance can be differentiated, but manufacturing complexity and process constraints increase
Solution Approach 1:
The patent replaces the mechanical/chemical implantation process with a deposition-based approach. Instead of using ion implantation to modify substrate properties, the invention uses physical vapor deposition or chemical vapor deposition to form distinct workfunction metal layers, simplifying the manufacturing process while achieving the same performance differentiation goal.
Solution Approach 2:
The invention changes the approach from modifying substrate parameters through implantation to modifying gate electrode parameters through deposition. By controlling the material composition and thickness of workfunction metal layers, the patent achieves performance differentiation through parameter control in a more manufacturable process.
3Adaptability or versatility
If additional mask operations are performed to differentiate workfunctions, then independent performance control is achieved, but manufacturing complexity and process steps increase
Solution Approach 1:
The patent merges the workfunction differentiation step with the existing gate electrode formation process. By integrating the selective deposition of different workfunction metal layers into the standard gate fabrication flow, the invention achieves independent performance control without adding separate mask and etch operations, thereby avoiding increased manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the independent targeting of performance for I/O and logic transistors, enhancing device efficiency and reducing manufacturing complexity by differentiating workfunctions without additional mask operations, thereby overcoming the limitations of conventional processes.
Implementation Method 1
The approach involves using a carbon hardmask to selectively etch and pattern different workfunction metal layers for I/O and logic transistors
Data Source
AI summary
Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.