Non-pullback Lead Pad Solder Standoff Manufacturing
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Solution Overview
Problem
Conventional semiconductor packages with no-lead (QFN) configurations have limited footprint reduction due to solder pads being pulled back from the package edge, which restricts the miniaturization of electronic systems.
Innovation Solution
A method for manufacturing semiconductor packages with solder standoffs where lead pads extend to the package edge, involving encapsulation of dies on a lead frame strip, forming channels between package sites, applying solder, and using a planarization tool to create a planar solder surface without singulating the packages initially, allowing for reduced footprint and elimination of etching or plating processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder pads are pulled back from the package edge, then manufacturing reliability is improved, but package footprint area increases
Solution Approach 1:
The patent applies preliminary action by forming channels between package sites before applying solder, and by using a planarization tool to create a planar solder surface before singulation. This sequence allows solder to extend to the package edge while maintaining manufacturing control, resolving the contradiction between footprint reduction and manufacturing reliability.
Solution Approach 2:
The patent introduces a planarization tool as an intermediary device that creates a planar solder surface. This intermediary enables the solder to extend to the package edge while maintaining a controlled, reliable surface for subsequent manufacturing steps, thus allowing footprint reduction without sacrificing manufacturing reliability.
2Area of stationary object
If lead pads extend to the package edge, then package footprint area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent extracts the etching and plating processes from the manufacturing sequence by using a planarization tool to create the solder surface. This elimination of complex chemical processes reduces manufacturing complexity while still allowing lead pads to extend to the package edge for footprint reduction.
Solution Approach 2:
The patent replaces chemical processes (etching and plating) with a mechanical planarization process. The planarization tool mechanically creates a planar solder surface, substituting complex chemical manufacturing steps with a simpler mechanical operation, thereby reducing manufacturing complexity while enabling edge-extending lead pads.
3Manufacturing precision
If etching and plating processes are used, then manufacturing precision is improved, but device complexity and environmental impact increase
Solution Approach 1:
The patent replaces chemical etching and plating processes with a mechanical planarization process. The planarization tool mechanically creates a precise, planar solder surface, achieving manufacturing precision without the complexity and environmental impact of chemical processes.
Solution Approach 2:
The patent uses a consumable planarization tool that is discarded after use, replacing expensive and environmentally harmful chemical etching and plating processes. This disposable mechanical tool achieves the required precision while simplifying the overall manufacturing process and reducing environmental impact.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of semiconductor packages with lead pads extending to the edge, achieving a smaller footprint without the need for etching or plating, and allows for a planarized solder standoff that enhances connectivity to larger electronic systems.
Implementation Method 1
The planarization tool comprises a device with a surface that promotes formation of a planar solder surface
Implementation Method 2
enclosing the solder between a planarization tool and at least one of the lead pad and die pad
Implementation Method 3
reflowing the solder to create a substantially planar solder standoff
Implementation Method 4
reflowing the solder
Data Source
AI summary
Disclosed herein is a method of manufacturing a semiconductor package with a solder standoff on lead pads that reach to the edge of the package (non-pullback leads). It includes encapsulating a plurality of die on a lead frame strip. The lead frame strip comprises a plurality of package sites, which further comprises a plurality of lead pads and a die pad. The method also includes forming a channel between the lead pads of nearby package sites without singulating the packages. Another step in the method includes disposing solder on the lead pads, the die pad, or the lead pads and the die pads without substantially covering the channel with solder. The manufacturing method further includes singulating the packages.