Non-uniform Back Layer for Semiconductor Chip Warpage Control
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Solution Overview
Problem
Semiconductor chip warpage due to coefficient of thermal expansion mismatch during cooling leads to unreliable bonding between the chip and the packaging substrate, causing uneven gaps and reduced reliability of solder connections.
Innovation Solution
A non-uniform thickness back layer is applied to the chip based on its warpage profile, with thicker layers on elements experiencing greater warpage to counteract stress and maintain chip flatness during reflow operations, using materials with a higher coefficient of thermal expansion than the chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a uniform thickness back layer is applied to the chip, then the manufacturing process is simple, but the chip warpage cannot be effectively controlled
Solution Approach 1:
The back layer is designed with non-uniform thickness, where the thickness varies across different regions of the chip based on the warpage profile. Specifically, the thickness t(x,y) is greater at regions experiencing higher warpage and smaller at regions with lower warpage, allowing localized compensation for stress distribution and achieving effective warpage control.
Solution Approach 2:
The back layer thickness parameter is changed from a constant uniform value to a spatially varying non-uniform value. The thickness distribution is determined by the warpage profile parameters, creating a gradient structure that optimizes stress compensation across different chip regions.
2Reliability
If the chip is directly bonded to the substrate without a back layer, then the assembly process is simple, but the solder connections become unreliable due to warpage
Solution Approach 1:
The back layer is applied to the chip before the bonding process to pre-compensate for warpage. By determining the warpage profile and calculating the required non-uniform thickness in advance, the back layer is prepared beforehand to counteract the expected thermal expansion mismatch during subsequent heating and cooling cycles, ensuring reliable solder connections.
Solution Approach 2:
The back layer acts as an intermediary element between the chip and the substrate, providing mechanical support and stress compensation. This intermediate layer absorbs and distributes thermal stresses, preventing direct transmission of warpage forces to the solder joints and maintaining connection reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces warpage by up to 30% and ensures reliable connections between the chip and the substrate by minimizing stress and maintaining chip flatness, thereby enhancing the reliability of the semiconductor assembly.
Implementation Method 1
using materials with a higher coefficient of thermal expansion than the chip
Data Source
AI summary
A semiconductor assembly includes a first substrate and a chip. The chip is coupled to and spaced apart from the substrate. Further, the chip has a first surface facing the substrate. The chip also has a warpage profile indicating stress imparted on the chip following a reflow operation. The assembly includes a back layer disposed on the chip on a second surface substantially opposite from the first surface. The back layer has a non-uniform thickness. Additionally, the thickness of the back layer on each of a plurality of elements of the chip is based on the warpage profile.