Non-uniform Dielectric Layer for Semiconductor Warpage Reduction
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Solution Overview
Problem
Conductive interconnection structures in semiconductor and interposer packages face reliability challenges due to non-optimal stress distribution and mismatch in the coefficient of thermal expansion (CTE) between semiconductor chips and their substrates, which complicates electrical connections and increases the size of compact electronic devices.
Innovation Solution
A method involving a substrate with a dielectric layer having a raised and lowered portion, where the conductive element is recessed below the height of the dielectric layer, and an electrically conductive structure couples the conductive element with conductive contacts, reducing the thickness of the dielectric layer to minimize stress and enhance interconnection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a uniform thickness dielectric layer is used to insulate conductive vias, then manufacturing simplicity is maintained, but significant stresses are present within the vias due to CTE mismatch between the conductive material and substrate
Solution Approach 1:
The patent applies local quality by creating a non-uniform dielectric layer where the thickness varies spatially. Specifically, the dielectric layer is thinner in regions adjacent to conductive vias and interconnection structures compared to other areas. This localized thickness variation reduces CTE mismatch stresses at critical locations without requiring complete redesign of the entire dielectric structure, thus improving via reliability while maintaining manufacturing feasibility through selective thickness control.
2Reliability
If the dielectric layer thickness is reduced to minimize stress, then via stress is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the dielectric layer into regions of different thicknesses, with thinner regions positioned strategically adjacent to conductive vias and interconnection structures. This segmentation allows stress reduction precisely where needed while maintaining adequate thickness in other areas for mechanical support and manufacturing robustness. The segmented approach enables graduated thickness control that balances stress reduction benefits with manufacturing precision requirements.
3Reliability
If conventional conductive interconnection structures are used, then electrical connections are established, but non-optimal stress distribution and CTE mismatch increase the size of the assembly
Solution Approach 1:
The patent applies parameter changes by modifying the dielectric layer thickness parameter to create a non-uniform profile. The dielectric layer thickness is reduced in specific regions adjacent to conductive interconnection structures, which alters the stress distribution parameters and reduces CTE mismatch effects. This parameter modification enables more compact interconnection structures with improved stress distribution, thereby reducing overall assembly size while maintaining electrical connection reliability.
Data Source
AI summary
A method of processing an interconnection element can include providing a substrate element having front and rear opposite surfaces and electrically conductive structure, a first dielectric layer overlying the front surface and a plurality of conductive contacts at a first surface of the first dielectric layer, and a second dielectric layer overlying the rear surface and having a conductive element at a second surface of the second dielectric layer. The method can also include removing a portion of the second dielectric layer so as to reduce the thickness of the portion, and to provide a raised portion of the second dielectric layer having a first thickness and a lowered portion having a second thickness. The first thickness can be greater than the second thickness. At least a portion of the conductive element can be recessed below a height of the first thickness of the second dielectric layer.