Non-uniform Floating Gate Coupling in Non-volatile Memory
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Solution Overview
Problem
As device miniaturization advances, the increased coupling between lines in non-volatile memory devices, such as EEPROM and flash memory, leads to reduced reliability in data read operations due to misreading caused by capacitive coupling between the select line and word lines.
Innovation Solution
The design includes a memory device with first and second floating gate patterns and dielectric patterns, where the area of overlap between the word lines and dielectric patterns is optimized to reduce coupling, with thicker device isolation regions and varying distances from the top surface of the floating gate patterns to the substrate, and the use of dummy word lines to minimize capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device miniaturization is implemented to increase storage density, then productivity and storage capacity are improved, but coupling between lines increases causing reading errors
Solution Approach 1:
The patent applies local quality by creating non-uniform dielectric patterns with different thicknesses at different locations. Specifically, the first dielectric pattern has a first thickness while the second dielectric pattern has a second thickness greater than the first thickness. This localized variation in dielectric properties allows different regions to have optimized coupling characteristics, enabling high storage density while maintaining reading accuracy by reducing capacitive coupling in critical areas.
Solution Approach 2:
The patent changes the dielectric thickness parameter to control coupling characteristics. By varying the dielectric thickness between different floating gate patterns, the patent optimizes the coupling ratio between control lines and floating gates. This parameter change enables the system to achieve both high storage density and reduced reading errors by adjusting the electrical coupling strength in different regions of the memory device.
2Ease of manufacture
If uniform dielectric patterns are used between word lines and floating gates, then manufacturing simplicity is maintained, but coupling ratio cannot be optimized leading to reading errors
Solution Approach 1:
The patent implements local quality by forming dielectric patterns with spatially varying thicknesses. The first dielectric pattern underlying the first word line has a first thickness, while the second dielectric pattern underlying the second word line has a second thickness greater than the first thickness. This non-uniform structure optimizes coupling ratios for different word lines, preventing reading errors while remaining compatible with standard semiconductor manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the coupling ratio between the select line and word lines, enhancing the reliability of data read operations and addressing the issue of misreading in non-volatile memory devices.
Implementation Method 1
the increased coupling between lines in non-volatile memory devices, such as EEPROM and flash memory, leads to reduced reliability in data read operations due to misreading caused by capacitive coupling between the select line and word lines
Data Source
AI summary
A memory device includes a substrate having an active region defined therein that extends linearly along a first direction. The device also includes a select line on the substrate and extending along a second direction to perpendicularly cross the active region, first and second floating gate patterns on the active region and spaced apart along the first direction, and first and second dielectric patterns on respective ones of the first and second floating gate patterns. The device further includes first and second word lines on respective ones of the first and second dielectric patterns and extending in parallel with the select line along the first direction. A first area of overlap of the first word line with the first floating gate pattern and the first dielectric pattern is less than a second area of overlap of the second word line with the second floating gate pattern and the second dielectric pattern. The first word line may be disposed between the select line and the second word line.