Output Driver Architecture Using Non-Uniform Slices for Fine Impedance Control
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Solution Overview
Problem
Conventional output drivers for integrated circuit devices face challenges in reducing the number of driver branches while maintaining high-resolution signaling, particularly as process geometries shrink, leading to increased die-area and power consumption due to the need for extensive pre-drivers and large transistor widths.
Innovation Solution
The implementation of differential-element sub-drivers with non-uniform conductances, where each sub-driver slice has a nominal impedance larger than the quantization step and increments differently, reduces the number of driver branches by using hierarchical or bilateral architectures, allowing for reduced transistor width and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional output drivers use uniform driver branches to meet specified output impedance and equalization range, then the driver achieves the required signaling performance, but the number of driver branches increases significantly leading to large die-area and high power consumption
Solution Approach 1:
The driver is segmented into two functional portions: a first portion dedicated to impedance calibration and a second portion dedicated to equalization. This segmentation allows each portion to be optimized independently, reducing the total number of driver branches required while maintaining both impedance calibration and equalization performance.
Solution Approach 2:
Different portions of the driver are assigned different functional qualities: the first portion is optimized for impedance calibration with appropriate resolution, while the second portion is optimized for equalization with its own resolution requirements. This local differentiation eliminates the need for all driver branches to have uniformly high resolution, thereby reducing overall die-area.
2Measurement precision
If conventional output drivers use uniform driver branches to maintain high-resolution signaling, then the driver achieves the required impedance calibration and equalization ranges, but the number of driver branches increases leading to high power consumption
Solution Approach 1:
The driver is divided into specialized portions where the first portion handles impedance calibration with its specific resolution needs, and the second portion handles equalization separately. This segmentation reduces the total number of high-resolution driver branches required, thereby lowering power consumption while maintaining calibration precision.
Solution Approach 2:
Each portion is given the local quality appropriate to its function: the impedance calibration portion has the resolution necessary for accurate impedance matching, while the equalization portion has resolution optimized for signal equalization. This prevents over-provisioning of resolution across all branches, reducing overall power consumption.
3Reliability
If conventional output drivers use uniform driver branches with sufficient width to meet process variation, then the driver maintains reliable signaling across process corners, but the transistor width must be large leading to increased die-area
Solution Approach 1:
By segmenting the driver into specialized portions for impedance calibration and equalization, each portion can be sized appropriately for its function rather than requiring all branches to be oversized to cover the full range of process variations. This reduces the required transistor width and die-area while maintaining reliability across process corners.
Solution Approach 2:
Each portion is designed with local quality appropriate to its function and process variation requirements. The impedance calibration portion can be optimized for robustness against process variation, while the equalization portion is optimized for signal integrity. This localized optimization reduces the need for uniformly large transistor widths across all branches.
Data Source
AI summary
High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested “DAC within a DAC” arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.