Non-Volatile C-Element Circuit for Power-Failure Data Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Asynchronous circuits lack non-volatile memory to retain data during power failures, and existing solutions often increase power consumption, making it challenging to develop compact circuits with this capability.
Innovation Solution
A gate C with cross-coupled inverters and programmable resistive elements, such as spin transfer torque or redox elements, that store data in resistive states, allowing for non-volatile memory using existing transistors during backup and restoration phases without significant power consumption increases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a non-volatile memory is added to gate C to enable data retention during power failures, then data retention capability is improved, but circuit complexity and power consumption increase
Solution Approach 1:
The patent combines the volatile storage function of gate C with non-volatile resistive memory elements by integrating them into a unified circuit structure. The resistive elements are coupled to the storage nodes of gate C through transistors, merging the temporary and permanent storage functions into a single system that achieves data retention without requiring a separate memory device.
Solution Approach 2:
The resistive elements serve multiple functions: they act as non-volatile storage elements during power failures, function as programmable resistors for data representation, and integrate with the existing gate C transistors to form a unified circuit. This multi-functionality reduces overall circuit complexity by eliminating the need for separate control logic and interface circuits.
2Reliability
If a non-volatile memory is added to gate C to enable data retention during power failures, then data retention capability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic backup phases where data is transferred from the volatile storage nodes to the non-volatile resistive elements. During normal operation, the circuit operates in low-power mode using only the volatile storage, and periodically performs backup operations to preserve data. This periodic action reduces average power consumption compared to continuous operation of non-volatile memory.
Solution Approach 2:
The circuit uses its own existing transistors to perform the backup operation by making them conductive during the backup phase. The existing transistor infrastructure is repurposed to write data to the resistive elements, eliminating the need for separate high-power write circuits and reducing overall power consumption.
3Device complexity
If existing transistors are used for backup operations in the non-volatile memory, then device complexity is reduced, but the transistors must operate in non-standard modes increasing design difficulty
Solution Approach 1:
The patent changes the operating parameters of existing transistors during backup phases by applying different logic levels to input nodes and making transistors conductive under specific conditions. The transistors operate in different regions (cutoff, linear, saturation) depending on the operational phase, allowing flexible control of data backup without requiring additional dedicated write transistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables data retention across power failures while maintaining low power consumption by utilizing existing transistors for write and restore operations, ensuring data integrity without excessive power usage.
Implementation Method 1
a first resistive element having a first terminal coupled to the first storage node; a second resistive element having a first terminal coupled to the second storage node, at least one of the first and second resistive elements being programmable to assume one of at least two resistive states, a data value being represented by the resistors relative of the first and second resistive elements
Implementation Method 2
at least one of the first and second resistive elements is of one of the following types: a spin transfer torque element having an anisotropy in the plane; a spin transfer torque element having an anisotropy perpendicular to the plane
Implementation Method 3
a redox element
Implementation Method 4
a ferroelectric element
Implementation Method 5
a phase change element
Data Source
Figure 1~2
Figure 3~5
Figure 6~7
AI summary
The invention relates to a circuit comprising: a gate C having first and second input nodes and first and second inverters (110, 112) cross-coupled between complementary first and second memory nodes (Q, Z), the second memory node (Z) forming an output node of the gate C; and a non-volatile memory comprising: a first resistive element (202) having a first terminal coupled to the first memory node (Q); a second resistive element (204) having a first terminal coupled to the second memory node (Z), at least one of the first and second resistive elements being programmable to take one of at least two resistive states (Rmin, Rmax), a second terminal of the first resistive element (202) being coupled to a second terminal of the second resistive element (204) via a first transistor (210); and a control circuit (232).