Non-Volatile Cache Direct Mapping for SSD Collision Reduction
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Solution Overview
Problem
Current data storage caching systems face inefficiencies due to cache collisions and high processing overhead in direct mapped, fully associative, and set associative caches, particularly in solid-state storage media.
Innovation Solution
A method and apparatus for caching data using a direct mapping module that associates logical addresses of a storage device with logical addresses of a non-volatile cache device, allowing for efficient mapping and eviction of data to maintain optimal storage capacity and reduce processing overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If direct mapped cache is used, then data retrieval speed is improved, but cache collisions increase
Solution Approach 1:
The patent segments the cache into multiple independent cache blocks, each capable of storing different data blocks from the backing store. This segmentation allows multiple data blocks to be cached simultaneously without colliding, as each cache block operates independently. The segmentation is achieved through physical separation of cache blocks and independent address mapping for each block.
Solution Approach 2:
The patent introduces a new dimension to cache addressing by using both a first address space for selecting cache blocks and a second address space for selecting data blocks within those cache blocks. This two-dimensional addressing scheme eliminates the one-dimensional collision problem by adding another layer of address differentiation, allowing precise selection of any cache block without interference from other blocks.
2Reliability
If fully associative cache is used, then cache collisions are reduced, but processing overhead increases
Solution Approach 1:
The patent segments the cache into multiple independent cache blocks, each with its own address mapping. This segmentation reduces the search space for data retrieval compared to fully associative caching, as data is only searched within the relevant cache block rather than across the entire cache. The segmentation maintains lower processing overhead while reducing collisions through independent block addressing.
Solution Approach 2:
The patent introduces an intermediary addressing layer between the backing store addresses and the physical cache locations. The first and second address spaces act as intermediaries that translate backing store addresses into specific cache block and data block selections, eliminating the need for complex search mechanisms while maintaining efficient data retrieval.
3Reliability
If set associative cache is used, then cache collisions increase, but processing overhead increases
Solution Approach 1:
The patent segments the cache into multiple independent cache blocks with independent address mappings. This segmentation approach is simpler than set associative caching as it eliminates the need for set indexing and tag comparison mechanisms. Each cache block can be directly accessed through its address, reducing both collisions and processing overhead simultaneously.
Solution Approach 2:
The patent uses intermediary address spaces as mediators between the backing store and the cache physical locations. The first address space selects cache blocks while the second address space selects data blocks within those blocks, providing direct addressing without the complexity of set associative indexing or tag searching mechanisms.
Data Source
AI summary
Apparatuses, systems, and methods are disclosed for caching data. A method includes directly mapping a logical address of a backing store to a logical address of a non-volatile cache. A method includes mapping, in a logical-to-physical mapping structure, the logical address of the non-volatile cache to a physical location in the non-volatile cache. The physical location may store data associated with the logical address of the backing store. A method includes removing the mapping from the logical-to-physical mapping structure in response to evicting the data from the non-volatile cache so that membership in the logical-to-physical mapping structure denotes storage in the non-volatile cache.