Nonvolatile Cache Memory Hierarchical Block Grouping for SSD Wear Reduction

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Solution Overview

Problem

Current cache memory systems in SSDs face inefficiencies in data management, leading to reduced performance and increased wear due to frequent garbage collection and limited cache capacity, as they lack effective mechanisms for selectively erasing data based on usage patterns and access frequencies.

Innovation Solution

A cache memory device with a nonvolatile cache memory system that employs a hierarchical block grouping structure, using FIFO-based selection to identify and erase blocks with low usage, allowing data to be dynamically reassigned and managed across multiple block groups based on access frequencies, thereby avoiding unnecessary garbage collection and optimizing cache capacity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If traditional cache memory systems are used in SSDs, then cache capacity is limited, but garbage collection frequency increases and performance decreases

Engineering Contradiction:
Improvecache capacityVSAvoidperformance
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The cache memory is divided into multiple block groups, where each block group contains several blocks. This segmentation allows independent management and erasure of individual block groups, enabling more efficient cache utilization and reducing the need for full cache garbage collection, thereby improving performance while maintaining effective cache capacity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically selects which block group to erase based on usage patterns and access frequencies. By adaptively managing cache blocks according to actual usage, the system optimizes cache capacity utilization and maintains high performance without being constrained by fixed cache size limitations.

Inventive Principle:
Principle #15Dynamics

2Reliability

If frequent garbage collection is performed, then cache capacity is maintained, but wear on the SSD increases

Engineering Contradiction:
Improvecache capacity maintenanceVSAvoidSSD lifespan
Core Design Contradiction:
ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The invention extracts and isolates specific block groups that require erasure based on usage patterns, rather than performing blanket garbage collection across the entire cache. This selective approach maintains cache capacity reliability while significantly reducing the frequency of erasure operations, thereby extending SSD lifespan.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system changes the erasure parameter from fixed periodic garbage collection to dynamic usage-based erasure. By monitoring access frequencies and usage patterns, the system determines when erasure is actually needed, reducing unnecessary wear while maintaining cache capacity.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If all blocks are treated equally in cache management, then management is simple, but cache efficiency decreases

Engineering Contradiction:
Improvemanagement complexityVSAvoidcache efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

Different block groups within the cache are managed differently based on their usage patterns. Frequently accessed blocks are preserved while infrequently used blocks are erased, creating local quality variations in cache management. This approach significantly improves cache efficiency without requiring complex global management mechanisms.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The cache management system transitions from static equal treatment of all blocks to dynamic differential management. By continuously monitoring usage patterns and adapting erasure decisions accordingly, the system achieves high cache efficiency with manageable complexity through automated usage-based differentiation.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10474569B2Information processing device including nonvolatile cache memory and processor
Publication Date: 2019.11.12 KIOXIA CORP
  • US10474569B2 patent drawing
  • US10474569B2 patent drawing
  • US10474569B2 patent drawing

AI summary

According to one embodiment, a cache memory device includes a nonvolatile cache memory, write unit, determination unit, selection unit, and erase unit. The nonvolatile cache memory includes a plurality of erase unit areas. Each of the erase unit areas includes a plurality of write unit areas. The write unit writes data to the nonvolatile cache memory. The determination unit determines whether the plurality of erase unit areas satisfy an erase condition or not. The selection unit selects an area to be erased from the plurality of erase unit areas when the plurality of erase unit areas satisfy the erase condition. The erase unit erases the data written to the area to be erased.