Nonvolatile Cache Memory Controller for Fast Data Persistence
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Solution Overview
Problem
Conventional techniques face challenges in achieving high-performance and high-reliability data persistence processing in online transaction processing systems that use byte-addressable high-speed nonvolatile memories like MRAM, PCM, or memristors, as they struggle to accelerate the commit process while ensuring atomicity and ordering due to the latency of cache flush commands and the need for explicit multiple version management.
Innovation Solution
A memory controller with a nonvolatile cache memory is connected to a processor via a cache coherence protocol, allowing immediate transfer and persistence of updated data to the nonvolatile cache memory, bypassing the need for writing to the nonvolatile main memory and ensuring atomicity and ordering through cache coherence protocols like MESIF or QPI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is written directly to nonvolatile main memory to ensure persistence, then data reliability is improved, but the commit process speed deteriorates due to writing latency
Solution Approach 1:
The patent segments the memory system into two distinct parts: a nonvolatile cache memory (fast, temporary storage) and a nonvolatile main memory (slow, permanent storage). This segmentation allows the system to handle different types of data access operations separately, using the cache for rapid commits and the main memory for permanent persistence, thereby resolving the contradiction between speed and reliability.
Solution Approach 2:
The nonvolatile cache memory acts as an intermediary between the processor and the nonvolatile main memory. It temporarily holds updated data that needs to be persisted, allowing the processor to complete commit operations quickly without waiting for the slower main memory write operations to complete, thus improving commit process speed while maintaining data reliability.
2Reliability
If cache flush commands are used to ensure data consistency, then data ordering is improved, but the commit process speed deteriorates due to command latency
Solution Approach 1:
The patent implements preliminary action by having the nonvolatile cache memory automatically receive and store updated data from the processor as it becomes available, without waiting for cache flush commands. The cache memory proactively manages data persistence, eliminating the need for slow cache flush operations while maintaining data ordering through its internal coherence protocol implementation.
Solution Approach 2:
The nonvolatile cache memory performs self-service by autonomously managing its own data coherence and persistence operations. It independently handles data updates from the processor and manages the timing of writes to the main memory, eliminating the need for the processor to issue cache flush commands and thereby improving commit process speed while ensuring data ordering.
3Reliability
If explicit multiple version management is implemented to ensure atomicity, then data reliability is improved, but the device complexity increases
Solution Approach 1:
The patent extracts the complex multiple version management logic from the processor and places it within the nonvolatile cache memory controller. This extraction allows the processor to focus on generating atomic transactions while the cache memory controller handles the complexity of version management, persistence timing, and coherence protocol implementation, thereby reducing overall system complexity while maintaining atomicity.
Solution Approach 2:
The nonvolatile cache memory serves as an intermediary that simplifies atomicity management by providing a coherent interface between the processor's atomic transactions and the main memory's persistence requirements. It automatically manages versioning and consistency without requiring the processor to implement complex version control mechanisms, thus improving atomicity assurance while reducing device complexity.
Data Source
AI summary
According to one embodiment, a memory controller includes a nonvolatile cache memory and a controller. The nonvolatile cache memory is configured to store a piece of data stored in a nonvolatile main memory connected to the memory controller. The controller is configured to control writing of data to the nonvolatile cache memory. The memory controller is connected to a processor via an interconnect that ensures a protocol indicating a procedure for preventing data inconsistency in a plurality of cache memories. The controller causes, after detecting that the processor has updated data corresponding to any area of the nonvolatile main memory using the protocol, the updated data to be transmitted to the memory controller and writes the updated data to the nonvolatile cache memory.