Non-Volatile Cache Control for Power Loss Data Recovery

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Solution Overview

Problem

Current information handling systems using volatile cache memories face data loss during power outages due to the reliance on battery-backed storage devices, which are unreliable, have limited shelf-life, and slow I/O speeds.

Innovation Solution

Implementing a method that utilizes a non-volatile memory to store 'dirty' data from a volatile cache during power loss and automatically restores it to the volatile memory upon power restoration, ensuring data integrity and efficiency by using a backup power supply and controller signals to manage data transfer between cache memories.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If battery-backed storage devices are used to protect volatile cache data during power loss, then data reliability is improved, but device complexity and cost increase

Engineering Contradiction:
Improvedata reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the backup power function from the storage device and places it specifically in the volatile cache memory. This allows the storage device to remain simple while the cache, which holds critical dirty data, has dedicated power protection through backup capacitors or batteries.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces non-volatile memory as an intermediary between the volatile cache and the storage device. This intermediary layer provides data persistence without requiring battery-backed storage devices, as the non-volatile memory inherently retains data without power.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If battery-backed storage devices are used to protect volatile cache data, then data integrity is improved, but I/O speed deteriorates

Engineering Contradiction:
Improvedata integrityVSAvoidI/O speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent segments the memory system into three distinct layers: volatile cache for high-speed temporary storage, non-volatile memory for persistent intermediate storage, and storage device for permanent storage. Each layer operates independently with optimized characteristics, allowing fast I/O through the volatile cache while ensuring data integrity through the non-volatile memory layer.

Inventive Principle:
Principle #1Segmentation

3Productivity

If write back mode is used to speed up data acknowledgment, then productivity is improved, but data loss risk increases during power outages

Engineering Contradiction:
ImproveproductivityVSAvoiddata loss risk
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements preliminary action by automatically writing dirty data from volatile cache to non-volatile memory upon detecting power loss. This preliminary backup ensures that even if the system crashes during write back operations, the dirty data is preserved and can be recovered after power restoration.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms through status flags that track the state of dirty data in the volatile cache. These flags provide feedback to the controller about which data needs to be restored after power loss, enabling automatic recovery without requiring complex error correction codes or redundant storage.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9003118B2Systems and methods for non-volatile cache control
Publication Date: 2015.04.07 DELL PROD LP
  • US9003118B2 patent drawing
  • US9003118B2 patent drawing
  • US9003118B2 patent drawing

AI summary

In some embodiments, a method for controlling a cache having a volatile memory and a non-volatile memory during a power up sequence is provided. The method includes receiving, at a controller configured to control the cache and a storage device associated with the cache, a signal indicating whether the non-volatile memory includes dirty data copied from the volatile memory to the non-volatile memory during a power down sequence, the dirty data including data that has not been stored in the storage device. In response to the received signal, the dirty data is restored from the non-volatile memory to the volatile memory, and flushed from the volatile memory to the storage device.