Non-Volatile Counter Layout for Memory Wear Balancing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory cells in electronic devices wear out quickly due to frequent program cycles, limiting the count of a counter implemented in such memory, especially as the least significant bit is updated more frequently, leading to corruption and unreliable counts.
Innovation Solution
Distributing the storage operations of a counter's low word across memory cells in a memory array and additional memory pages, with the location determined by upper bits, allowing for balanced wear across cells by programming or erasing based on bit transitions, and using redundant memory pages for error protection against power failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a binary counter is implemented using non-volatile memory cells, then the counter can store its value in memory, but the memory cells wear out and become unreliable after a limited number of program cycles
Solution Approach 1:
The counter is divided into multiple segments (counter0, counter1, counter2, etc.), each stored in separate memory locations. This segmentation allows the system to rotate which counter segment is actively updated, distributing the wear across multiple memory cells rather than concentrating it in a single cell storing the least significant bit.
Solution Approach 2:
The system dynamically switches between different counter segments based on a rotation counter. The active counter segment changes over time, which dynamically redistributes the program cycle workload across different memory cells, preventing any single cell from reaching its wear limit prematurely.
2Measurement precision
If the least significant bit is updated for each count, then the counter can accurately track each increment, but the memory cell storing the least significant bit wears out or becomes unreliable sooner than other memory cells
Solution Approach 1:
The counter is divided into multiple segments (counter0, counter1, counter2, etc.), each stored in separate memory locations. This segmentation allows the system to rotate which counter segment is actively updated, distributing the wear across multiple memory cells rather than concentrating it in a single cell storing the least significant bit.
Solution Approach 2:
The system dynamically switches between different counter segments based on a rotation counter. The active counter segment changes over time, which dynamically redistributes the program cycle workload across different memory cells, preventing any single cell from reaching its wear limit prematurely.
3Reliability
If a non-volatile counter is implemented to count power-on events or prints, then the counter provides persistent storage, but the counter cannot count higher than the number of program cycles the memory cell can withstand
Solution Approach 1:
The counter is divided into multiple segments (counter0, counter1, counter2, etc.), each stored in separate memory locations. This segmentation allows the system to rotate which counter segment is actively updated, distributing the wear across multiple memory cells rather than concentrating it in a single cell storing the least significant bit.
Solution Approach 2:
The system dynamically switches between different counter segments based on a rotation counter. The active counter segment changes over time, which dynamically redistributes the program cycle workload across different memory cells, preventing any single cell from reaching its wear limit prematurely.
Data Source
Figure 1
Figure 2
Figure 3A
AI summary
A method for implementing a non-volatile counter using non-volatile memory is disclosed. In an embodiment, the method involves distributing operations for storing a low word of a counter in non-volatile memory across memory cells in a memory array in the non-volatile memory, and storing additional bits of the counter in the non-volatile memory in memory cells outside of the memory array, wherein the location in the memory array at which the low word is stored is determined for each count based on the upper bits of the counter.