Nonvolatile DIMM Controller Latency Management
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Solution Overview
Problem
As the number of memory devices coupled to a single controller increases, the number of required signal lines also increases, complicating system design and increasing fabrication costs, especially when performing backup and restoration operations due to power failures in nonvolatile dual in-line memory modules.
Innovation Solution
A nonvolatile dual in-line memory system that allows individual access to volatile memory devices with a reduced number of signal lines by using a controller with backup and restoration logic, which sets different command address latencies for volatile memory devices to manage data backup and restoration operations efficiently, and includes logic for distributed refresh operations and power mode management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of memory devices coupled to a single controller increases, then the data backup and restoration capability is improved, but the number of required signal lines increases, complicating system design and increasing fabrication costs
Solution Approach 1:
Multiple volatile memory devices share common signal lines (address bus, data bus, control bus) that are multiplexed in time. The controller sequentially selects different memory devices using chip select signals and command address latency settings, allowing one set of signal lines to serve multiple devices without simultaneous conflicts.
Solution Approach 2:
The controller dynamically assigns different command address latency values to different volatile memory devices, enabling flexible and selective access to individual devices sharing the same signal lines. This dynamic timing control allows the system to adapt which device responds to commands at any given moment.
2Ease of operation
If separate control buses and data buses are provided for each memory device, then independent control capability is improved, but the number of signal lines increases
Solution Approach 1:
Multiple memory devices share common address buses, data buses, and control buses. The controller maintains independent control capability by using chip select signals and command address latency settings to selectively activate specific devices, eliminating the need for separate dedicated signal lines for each device.
Solution Approach 2:
A single set of signal lines serves multiple functions by sequentially connecting to different memory devices. The same address bus, data bus, and control bus are universally used across all volatile memory devices, with device selection achieved through timing and chip select mechanisms rather than dedicated lines.
3Device complexity
If signal lines are shared among multiple memory devices, then the number of signal lines is reduced, but the ability to independently access individual devices decreases
Solution Approach 1:
The controller uses dynamic command address latency assignment to enable independent access to each shared memory device. By setting different latency values for different devices, the controller determines which device becomes accessible at any given moment, maintaining independent access capability despite shared signal lines.
Solution Approach 2:
The controller preliminarily selects which memory device should be accessed by setting appropriate command address latency values before issuing commands. This preliminary selection ensures that only the intended device responds to subsequent commands on the shared signal lines, preventing conflicts and enabling independent access.
Data Source
AI summary
A nonvolatile memory module includes a plurality of volatile memory devices sharing a data bus through which data is transmitted and a control bus through which a command and an address are transmitted; at least one nonvolatile memory device; and a controller including a backup logic which backs up data stored in the plurality of volatile memory devices when a fail in power of the host is detected or a backup operation is instructed from the memory controller of the host, wherein the backup logic sets a command address latency (CAL) of one among the plurality of volatile memory devices to a first value, and sets a command address latency of remaining volatile memory devices to a second value different from the first value.