Nonvolatile DIMM Power-Down Interrupt Logic
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Solution Overview
Problem
In memory systems, as the number of memory devices increases, so does the complexity and cost due to the need for a large number of wiring lines, making it difficult to manage and maintain efficient operations, especially during power failures and recovery.
Innovation Solution
A nonvolatile dual in-line memory system that allows independent access to volatile memory devices using a shared data and control bus, with a controller managing backup and restoration operations by setting different command address latencies for each device to reduce wiring requirements and ensure efficient power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If separate control buses and data buses are provided for each memory device, then independent control operations can be performed, but the number of wiring lines increases and system complexity increases
Solution Approach 1:
The patent combines multiple control buses (CMD0/ADDR0 and CMD1/ADDR1) into a single shared control bus (CMD/ADDR bus), and merges multiple data buses (DATA0 and DATA1) into a single shared data bus (DATA bus). This merging reduces the number of wiring lines while maintaining the ability to independently control multiple memory devices through different chip select signals (CS0 and CS1) that are selectively activated based on the memory device being accessed.
2Ease of operation
If separate control buses and data buses are provided for each memory device, then independent control operations can be performed, but fabrication cost increases
Solution Approach 1:
The patent merges multiple separate bus lines into shared buses, directly reducing the total number of wiring lines that need to be fabricated. This reduction in wiring lines lowers fabrication complexity and cost, while the shared buses are controlled by chip select signals that enable independent operation of each memory device, thus maintaining operational independence without the high cost of fully separate buses.
3Quantity of substance
If the number of memory devices is increased, then storage capacity is improved, but the number of wiring lines increases making system design more difficult
Solution Approach 1:
The patent implements a universal shared control bus (CMD/ADDR bus) and shared data bus (DATA bus) that can serve multiple memory devices (MD0, MD1, and potentially more). The chip select signals (CS0, CS1) provide a mechanism to selectively activate specific memory devices, allowing the same bus infrastructure to be universally used for multiple devices without increasing wiring complexity. This multi-functional bus design enables easy expansion of storage capacity while keeping system design manageable.
Data Source
AI summary
A nonvolatile memory module includes volatile memory devices; a nonvolatile memory device; and a controller suitable for backing up data stored in the volatile memory devices or restoring data backed up in the nonvolatile memory device, according to a fail/recovery of power of the host, the controller including a power-down interrupt logic which interrupts a backup operation when the power of the host is recovered while performing the backup operation, the power-down interrupt logic including: a logic which determines whether sufficient erased blocks exist in the nonvolatile memory device; a logic which erases a new block when the sufficient erased bocks do not exist; and an interrupt backup logic which backs up a volatile memory device having data corresponding to the erased block, when a fail in the power of the host is detected or a backup operation is instructed from the host.