Non-Volatile DRAM Cell Using Floating Gate Transistor
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Solution Overview
Problem
Current memory technologies face challenges in creating a non-volatile DRAM cell that offers fast random access like volatile DRAM while retaining data like non-volatile memory, with existing solutions often requiring complex system designs and affecting capacitor voltages during program or erase operations.
Innovation Solution
A non-volatile DRAM cell comprising a NMOS pass-gate transistor with a floating gate, a metal-insulator-metal capacitor, and a control gate, where data is stored in both the capacitor and the floating gate, allowing for independent row operations without affecting neighboring rows, using Fowler-Nordheim tunneling for programming and gate-induced-drain-lowering assisted band-to-band tunneling for erasing, while maintaining the same sense amplifier for both DRAM and NVM read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a non-volatile memory cell is formed by merging EEPROM cell with DRAM cell (as in prior art), then data retention capability is improved, but cell complexity and silicon footprint increase
Solution Approach 1:
The patent merges a DRAM cell (1T1C) with a non-volatile memory element (floating gate transistor) to create a unified non-volatile DRAM cell. The floating gate transistor serves dual purposes: as the pass gate for DRAM operation and as the non-volatile storage element, eliminating the need for separate EEPROM transistor and reducing overall cell complexity while maintaining data retention capability
Solution Approach 2:
The floating gate transistor is designed to perform multiple functions: it acts as the pass gate transistor for DRAM read/write operations, provides non-volatile data storage through its floating gate, and enables both volatile and non-volatile memory modes from a single cell structure, thereby reducing the need for additional components
2Productivity
If program or erase operations are performed on selected rows in non-volatile DRAM, then data is updated in target cells, but capacitor voltages in neighboring rows are affected
Solution Approach 1:
The patent applies segmentation by confining program and erase operations to specifically selected rows only. Through precise control of word line voltages, the patent ensures that high voltage stress and charge injection effects are localized to the targeted row, preventing disturbance to capacitors in non-selected rows and enabling independent row operations without affecting neighboring rows
3Adaptability or versatility
If non-volatile and volatile memory are used separately in computer systems, then each memory type can be optimized for its specific application, but system design becomes more complicated due to different interface and control requirements
Solution Approach 1:
The patent creates a universal memory cell that can operate in both volatile DRAM mode and non-volatile memory mode. The same cell structure, with its floating gate transistor and capacitor, can be used for fast random access operations or for permanent data retention, allowing the system to use a single memory type for multiple applications and reducing interface and control complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables fast read and write access similar to DRAM, with data retention capabilities of non-volatile memory, minimizing page size for program/erase operations and improving read/write tolerance by allowing independent row operations, thus reducing the need for array-wide erase/program cycles.
Implementation Method 1
data is stored in both the capacitor and the floating gate
Implementation Method 2
using Fowler-Nordheim tunneling for programming
Implementation Method 3
gate-induced-drain-lowering assisted band-to-band tunneling for erasing
Data Source
AI summary
A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by negatively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully discharged. The pass-gate transistor is activated and if the pass-gate transistor is programmed it does not turn on and if it is erased, it turns on. Charge is shared on the complementary pair of precharged bit lines connected to the non-volatile DRAM cell and its associated Dummy non-volatile DRAM cell. A sense amplifier detects the difference in the data state stored in the pass-gate transistor. The program and erase of the non-volatile DRAM cell is accomplished by charge injection from the associated bit line of the non-volatile DRAM cell.