Non-Volatile DRAM Cell Using PMOS Pass-Gate and Floating Gate
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Solution Overview
Problem
Current non-volatile DRAM technologies face challenges in achieving fast random access and data retention while maintaining compatibility with DRAM processes, as they often require significant changes to the memory cell structure and sensing schemes, leading to increased complexity and reduced endurance.
Innovation Solution
A non-volatile DRAM cell design incorporating a PMOS pass-gate transistor with a floating gate and a metal-insulator-metal capacitor, allowing for data storage in both the capacitor and floating gate without altering the common-plate voltage of the cell capacitor, enabling fast read/write access and data retention with minimal changes to the DRAM process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a non-volatile memory cell structure is used (e.g., merging EEPROM cell with DRAM cell), then data retention capability is improved, but device complexity increases and manufacturing precision requirements worsen
Solution Approach 1:
The patent segments the memory system into two independent parts: a volatile DRAM section for fast access and a non-volatile memory section for data retention. This segmentation allows each part to be optimized independently, avoiding the complexity of merged cell structures while achieving both fast access and data retention capabilities.
Solution Approach 2:
The patent creates a memory system that can operate in multiple modes (volatile mode for fast access, non-volatile mode for data retention) using a unified architecture. The same memory controller and interface handle both modes, providing multi-functionality without requiring separate complex cell structures for each mode.
2Adaptability or versatility
If different memory types (non-volatile and volatile) are combined in one system, then both fast access and data retention are achieved, but interface and control complexity increases
Solution Approach 1:
The patent implements a universal memory controller that manages both volatile and non-volatile memory operations through a single interface. The controller can dynamically switch between DRAM mode and non-volatile memory mode, handling read, write, and erase operations for both memory types without requiring separate control logic or interfaces.
Solution Approach 2:
The patent merges the volatile DRAM array and non-volatile memory array into a single unified memory device with shared control logic, address decoding, and data I/O interfaces. This consolidation reduces the overall interface and control complexity compared to having separate memory devices while maintaining dual-mode operation capabilities.
3Reliability
If conventional non-volatile memory programming techniques are used, then data retention is achieved, but access speed deteriorates
Solution Approach 1:
The patent segments data storage into two locations: the volatile DRAM section for frequently accessed data requiring fast read/write operations, and the non-volatile memory section for data requiring permanent retention. This segmentation allows the system to achieve both fast access speeds for active data and permanent retention for stored data, avoiding the speed penalty of conventional non-volatile memory for all operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design provides fast read/write access similar to DRAM while retaining data like a non-volatile memory, reducing the page size of program/erase operations and enhancing endurance by allowing independent row operations, thus improving overall memory performance.
Implementation Method 1
A non-volatile DRAM cell design incorporating a PMOS pass-gate transistor with a floating gate and a metal-insulator-metal capacitor
Implementation Method 2
a metal-insulator-metal capacitor, allowing for data storage in both the capacitor and floating gate
Data Source
AI summary
A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by positively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully charged. The pass-gate transistor is activated and if the pass-gate transistor is erased it does not turn on and if it is programmed, it turns on. Charge is shared on the complementary pair of pre-charged bit lines connected to the non-volatile DRAM cell and its associated Dummy non-volatile DRAM cell. A sense amplifier detects the difference in the data state stored in the pass-gate transistor. The program and erase of the non-volatile DRAM cell is accomplished Gate-induced drain-lowering (GIDL) assisted band-to-band tunneling and Fowler-Nordheim tunneling respectively. Programming or erasing a selected row of cells does not affect the data states of the cells in the unselected rows.