Nonvolatile FPGA Configuration Memory for Fast Rewriting
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Solution Overview
Problem
Current Field Programmable Gate Arrays (FPGAs) face challenges with high power consumption and large footprint due to SRAM, and limited reconfigurability with DRAM, which requires frequent refresh operations and has destructive writing methods.
Innovation Solution
A reconfigurable integrated circuit device utilizing a nonvolatile memory transistor with a switch circuit and data supply circuit, allowing for repeatable writing and low power consumption, featuring a MONOS-type memory transistor with a charge storage layer and a switch circuit that enables high-speed writing and erasing without damaging the transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SRAM is used to store configuration information, then high-speed writing is achieved, but power consumption increases and device footprint becomes large
Solution Approach 1:
The patent changes the fundamental parameter of memory volatility by using nonvolatile memory transistors instead of volatile SRAM cells. This allows the memory to retain data without continuous power supply, eliminating the need for constant refresh operations and significantly reducing power consumption while maintaining reconfigurability capability
Solution Approach 2:
The patent employs a composite memory structure combining nonvolatile memory transistors with charge storage layers (such as nitride layers or oxide layers) to create a hybrid memory system that integrates the advantages of both volatile and nonvolatile memory characteristics, achieving high-speed writing similar to SRAM while maintaining nonvolatile data retention
2Speed
If SRAM is used to store configuration information, then high-speed writing is achieved, but device footprint becomes large
Solution Approach 1:
The patent changes the memory cell structure from six-transistor SRAM cells to single-transistor nonvolatile memory cells with charge storage layers. This structural parameter change reduces the memory cell area by approximately 6 times while maintaining writing speed performance, thereby significantly reducing the overall device footprint of the FPGA
Solution Approach 2:
The use of composite materials including ultrathin nitride layers or oxide layers as charge storage media enables the creation of compact memory cells with high storage density. These composite structures allow for smaller cell dimensions while maintaining electrical performance and writing speed characteristics
3Use of energy by moving object
If flash memory is used to store configuration information, then power consumption is reduced, but writing and erasing time increases
Solution Approach 1:
The patent modifies the memory transistor structure by replacing conventional flash memory transistors with nonvolatile memory transistors that have modified gate structures and charge storage layers positioned closer to the channel. This structural parameter change enables faster charge injection and extraction processes, reducing writing and erasing times from milliseconds (flash memory) to microseconds or nanoseconds while maintaining low power consumption characteristics
4Area of stationary object
If DRAM is used to store configuration information, then footprint is reduced and writing speed is high, but frequent refresh operations are required
Solution Approach 1:
The patent fundamentally changes the memory volatility parameter by using nonvolatile memory transistors with charge storage layers that can trap and retain charges indefinitely without power supply. This eliminates the need for periodic refresh operations required by DRAM, removing the associated time loss and power consumption while maintaining the small footprint advantage of DRAM
5Duration of action of stationary object
If destructive writing method is used to make DRAM nonvolatile, then data retention is improved, but reconfigurability is lost
Solution Approach 1:
The patent changes the physical structure of the memory transistor by introducing nonvolatile memory transistors with charge storage layers that can be electrically programmed and erased without physical damage. This allows the transistor to remain functional and reusable, enabling multiple write-erase cycles and maintaining reconfigurability while achieving nonvolatile data retention, unlike destructive methods that permanently damage the transistor gate
Data Source
AI summary
A reconfigurable integrated circuit device includes a memory unit for storing configuration information. The memory unit has a nonvolatile memory transistor having a gate connected to a first wire, a first terminal connected to a second wire, and a second terminal connected to a third wire. The memory unit also includes a switch circuit connected to the third wire. The switch circuit alters the configuration of the integrated circuit device by, for example, opening and closing to make wiring connections or disconnections. The integrated circuit device additionally includes a data supply circuit for supplying bit data and a first power supply circuit for supplying voltages to the first wire for storing bit data in the first nonvolatile memory transistor and for storing bit data as a charge level on the third wire.