Non-Volatile FPGA Logic Drive to Cut ASIC NRE Costs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high cost and inefficiencies of transitioning from Field Programmable Gate Array (FPGA) IC chips to Application Specific IC (ASIC) or Customer-Owned Tooling (COT) chips for semiconductor applications, particularly in advanced technology nodes, hinder innovation and increase Non-Recurring Engineering (NRE) costs, leading to a barrier for adopting new semiconductor technologies.
Innovation Solution
Utilizing standardized commodity logic drives comprising plural FPGA IC chips with non-volatile random access memory cells, which can be field programmed for various applications, reducing NRE costs and enabling efficient workload processing by allowing developers to write software codes for innovative algorithms and architectures, similar to commodity DRAM or NAND flash memory IC chip businesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA IC chips are used for field programming purposes, then adaptability and versatility are improved, but device complexity and fabrication cost increase
Solution Approach 1:
The patent applies universality by using standardized commodity FPGA IC chips that can be field-programmed for multiple different applications and algorithms. The FPGA chips serve as universal computing devices that can be reconfigured via software codes to perform various logic functions, replacing the need for multiple specialized ASIC chips for different applications.
Solution Approach 2:
The patent applies parameter changes by utilizing advanced semiconductor technology nodes (e.g., 16nm, 14nm, 12nm, 10nm, 7nm, 5nm, 3nm) to reduce the physical size of FPGA chips while maintaining or improving their field programming capabilities. The transition to advanced nodes changes the physical parameters of the chips, enabling smaller size with enhanced functionality.
2Productivity
If ASIC or COT chips are used for expanded applications, then productivity and performance are improved, but Non-Recurring Engineering costs increase greatly
Solution Approach 1:
The patent applies this principle by using standardized commodity FPGA IC chips instead of expensive custom ASIC chips. The FPGA chips can be programmed and reprogrammed for different applications, eliminating the need for costly NRE investments in custom chip design. The chips serve as disposable or reusable universal platforms that don't require million-dollar mask sets for each application.
Solution Approach 2:
The patent uses universal FPGA chips that can handle multiple applications through field programming, replacing the need for application-specific ASIC chips. This universality maintains productivity across different workloads while eliminating the high NRE costs associated with creating custom chips for each application.
3Manufacturing precision
If advanced semiconductor technology nodes are used, then manufacturing precision and performance are improved, but Non-Recurring Engineering costs increase by more than US $5M
Solution Approach 1:
The patent applies universality by using the same advanced node FPGA chip design for multiple different applications and markets. Instead of creating custom ASIC chips at advanced nodes for each application (requiring separate million-dollar mask sets), the same standardized FPGA chip can be field-programmed to serve various purposes, amortizing the advanced node manufacturing costs across multiple applications.
Solution Approach 2:
The patent applies copying by using standardized commodity FPGA IC chip designs that can be replicated and distributed without the need for expensive custom mask sets. The same chip design serves as a template that can be copied and programmed for different applications, avoiding the need to pay NRE costs for each individual application.
Data Source
AI summary
A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.