Non-Volatile FPGA Logic Drive for Lower NRE at Advanced Nodes

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Solution Overview

Problem

The high cost and complexity of transitioning from Field Programmable Gate Array (FPGA) IC chips to Application Specific IC (ASIC) or Customer-Owned Tooling (COT) chips, particularly in advanced semiconductor technology nodes, hinder innovation and scalability due to larger chip size, higher fabrication costs, and increased Non-Recurring Engineering (NRE) expenses.

Innovation Solution

Utilizing standardized commodity logic drives comprising multiple FPGA IC chips, which can be field programmed for various applications, reducing NRE costs by allowing innovators to develop software codes on these drives, thus lowering the barrier for implementing innovations in advanced technology nodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If FPGA IC chips are used for a given application, then adaptability and ease of operation are improved, but chip size, fabrication cost, and power consumption increase compared to ASIC or COT chips

Engineering Contradiction:

ImproveadaptabilityVSAvoidchip size

Core Design Contradiction:

Adaptability or versatilityVSArea of moving object

Solution Approach 1:

The patent segments the logic drive into multiple standardized commodity FPGA IC chips organized in a multi-chip package. Each chip can be independently programmed and configured, allowing the system to be divided into functional modules that can be optimized separately while maintaining overall adaptability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent creates a universal logic drive platform that can serve multiple applications through field programming. The standardized commodity FPGA chips are designed to be reconfigurable for different logic functions, enabling a single hardware platform to perform multiple roles similar to how universal storage drives handle different data types.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If FPGA IC chips are used for a given application, then adaptability is improved, but fabrication cost increases compared to ASIC or COT chips

Engineering Contradiction:

ImproveadaptabilityVSAvoidfabrication cost

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent uses standardized commodity FPGA IC chips that are mass-produced copies of a proven design. These standardized chips leverage existing fabrication processes and supply chains, reducing per-unit costs compared to custom ASIC designs while maintaining programmability for different applications.

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The patent changes the operational parameters of the FPGA chips through field programming rather than requiring different fabrication processes. By using configuration memory and programmable logic elements, the same physical chip can be reconfigured for different applications, avoiding the high NRE costs of creating multiple ASIC variants.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If advanced semiconductor technology nodes are used, then performance and integration density are improved, but NRE cost increases greatly

Engineering Contradiction:

ImproveperformanceVSAvoidNRE cost

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent performs the complex design and fabrication work in advance by creating standardized commodity FPGA chips at advanced technology nodes. Once these chips are manufactured, they can be deployed repeatedly without incurring additional NRE costs, amortizing the initial investment across many units and applications.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent treats individual FPGA chips as replaceable, standardized components rather than expensive custom ASICs. The lower per-chip cost of standardized FPGAs allows for a more economical approach where chips can be upgraded or replaced more easily, reducing the financial risk associated with adopting advanced technology nodes.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

4Area of moving object

If ASIC or COT chip design is implemented, then chip size and power consumption are reduced for a given application, but adaptability and ease of operation decrease

Engineering Contradiction:

Improvechip sizeVSAvoidadaptability

Core Design Contradiction:

Area of moving objectVSAdaptability or versatility

Solution Approach 1:

The patent introduces dynamic reconfigurability to the system by using field-programmable logic. The FPGA chips can be reconfigured in the field to adapt to different applications and requirements, providing a dynamic solution that bridges the gap between the fixed, optimized nature of ASICs and the flexible but larger FPGA architecture.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20250337416A1Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells

Publication Date: 2025.10.30 ICOMETRUE CO LTD

AI summary

A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.