Non-Volatile FPGA Logic Drive for Low-NRE Reconfigurable ICs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The transition from Field Programmable Gate Array (FPGA) IC chips to Application Specific IC (ASIC) or Customer-Owned Tooling (COT) chips is hindered by higher costs, power consumption, and lower performance, leading to increased Non-Recurring Engineering (NRE) costs for advanced semiconductor technology nodes, which limits innovation and makes it difficult for innovators to utilize advanced IC technology nodes.
Innovation Solution
A standardized commodity logic drive using multiple FPGA IC chips for various applications, reducing NRE costs by allowing developers to purchase and program the logic drive with software codes, similar to commodity DRAM or flash memory IC chips, and providing a public innovation platform for innovators to implement ideas using advanced IC technology nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA IC chips are used for logic functions, then adaptability and ease of operation are improved, but device complexity, power consumption, and fabrication cost increase
Solution Approach 1:
The patent uses memory cells to store configuration data that copies the desired logic circuit behavior, allowing the FPGA to be reprogrammed without physical hardware changes. This copying approach enables adaptability while keeping the physical device structure simple and standardized
Solution Approach 2:
The patent creates a universal FPGA device that can perform multiple logic functions through software configuration. The same physical device can be reconfigured for different applications, eliminating the need for multiple specialized hardware devices and reducing overall system complexity
2Power
If ASIC or COT IC chips are used for expanded applications, then performance and power efficiency are improved, but NRE cost and fabrication cost increase significantly
Solution Approach 1:
The patent employs standardized, mass-producible FPGA devices that can be manufactured at low cost using existing production lines. These devices replace expensive, custom-designed ASICs for applications where high volume production is needed, making the system economically viable without requiring costly NRE investments
Solution Approach 2:
The patent changes the configurability parameter of the device, allowing a single standardized hardware design to serve multiple applications through software reconfiguration. This eliminates the need for costly mask sets and NRE processes required for ASIC production, as the same physical device can be reprogrammed for different functions
3Productivity
If advanced semiconductor technology nodes are used, then performance and integration density are improved, but NRE cost increases greatly
Solution Approach 1:
The patent segments the functionality of the device into fixed hardware architecture and configurable logic elements. This allows the use of advanced technology nodes for the configurable portions while keeping the overall device structure standardized and compatible with existing manufacturing processes, reducing NRE costs
Solution Approach 2:
The patent uses memory cells to store configuration data that defines the logic circuit behavior at advanced technology nodes. This copying mechanism allows standardized devices to be manufactured at advanced nodes without requiring costly custom mask sets, as the configuration is stored in reconfigurable memory rather than hardwired through expensive photolithography
Data Source
AI summary
A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.