Nonvolatile FPGA with Voltage Conversion for High-Speed Operation
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Solution Overview
Problem
Conventional nonvolatile FPGAs employing antifuse devices face limitations due to high voltage requirements for programming, which reduces operational speed and prevents the use of multiple memory architectures, as high voltage signals cannot be directly amplified by low voltage driven CMOS circuits without risking transistor breakdown.
Innovation Solution
The design incorporates a programmable logic circuit with a configuration that allows for a program voltage Vpp to be applied without breaking down the gate insulating film of transistors, enabling direct amplification of signals and high-speed operation by using cut-off transistors and CMOS inverters that operate with the power supply voltage Vdd, and includes a multi-context FPGA capability for dynamic reconfiguration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage is applied to write data in antifuse devices, then nonvolatile storage is achieved, but operational speed decreases because low voltage CMOS circuits cannot directly amplify high voltage signals
Solution Approach 1:
The patent introduces a voltage conversion mechanism that acts as an intermediary between the high voltage write operation and the low voltage read operation. The programmable device breakdown during write creates a conductive path that can be controlled by low voltage signals during read operations, allowing CMOS circuits to directly amplify signals without voltage level conflicts.
Solution Approach 2:
The patent changes the voltage parameter dynamically - high voltage is applied only during the write operation to break down the programmable device, while low voltage is used during normal operation and read operations. This parameter change resolves the contradiction by separating the voltage requirements of different operational phases.
2Reliability
If conventional antifuse devices are used, then nonvolatile data storage is achieved, but multiple memory architecture cannot be implemented
Solution Approach 1:
The patent designs the programmable logic circuit to serve multiple functions - it can operate as a switch block for routing signals and as a memory element for nonvolatile storage. The same programmable device structure enables both routing functionality and memory functionality, allowing multiple memory architectures to be implemented within the FPGA.
Solution Approach 2:
The patent introduces dynamic reconfiguration capability where the programmable devices can be programmed at different times to create different memory architectures. The configuration memories can be programmed after the FPGA is manufactured, allowing the same hardware to support multiple memory configurations depending on application requirements.
3Adaptability or versatility
If switch blocks are replaced with antifuse devices for nonvolatile operation, then reconfigurability is reduced, but if switch blocks are maintained for full reconfigurability, then nonvolatile capability is lost
Solution Approach 1:
The patent segments the FPGA into different functional regions - some areas use programmable devices for nonvolatile routing (switch block functionality) while other areas use configuration memories for reconfigurable logic blocks. This segmentation allows simultaneous achievement of nonvolatile operation in routing and reconfigurability in logic functions.
Solution Approach 2:
The patent performs preliminary programming of the programmable devices during manufacturing or initial configuration to establish the nonvolatile routing structure. This preliminary action creates a fixed nonvolatile backbone that supports subsequent reconfiguration of logic blocks without compromising the nonvolatile capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for high-speed operation of FPGAs without increasing circuit area and enables the use of multiple memory architectures, improving integration and operational efficiency by allowing direct amplification of signals on wiring lines and enabling instantaneous switching between different logic functions.
Implementation Method 1
a programmable device with a first terminal and a second terminal, the first terminal connecting to one of the source and the drain of the first transistor, the second terminal being connected to one of the second wiring lines
Data Source
AI summary
A programmable logic circuit includes: first to third wiring lines, the second wiring lines intersecting with the first wiring lines; and cells provided in intersecting areas, at least one of cells including a first transistor and a programmable device with a first and second terminals, the first terminal connecting to one of a source and a drain of the first transistor, the second terminal being connected to one of the second wiring lines, the other of the source and the drain being connected to one of the first wiring lines, and a gate of the first transistor being connected to one of the third wiring lines. One of source and drain of each of the first cut-off transistors is connected to the one of the second wiring lines, and an input terminal of each of first CMOS inverters is connected to the other of the source and the drain.