Non-volatile Inverter With Segmented Tunneling Insulation
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Solution Overview
Problem
Current non-volatile memory devices, such as polysilicon-oxide-nitride-oxide-silicon (SONOS) memory devices, face challenges with low operating speed and high power consumption due to the thickness of the tunneling insulation layer, which can lead to direct tunneling and stress-induced leakage current issues when trying to improve speed.
Innovation Solution
The development of a non-volatile inverter with a charge trap layer and a threshold voltage switching material, such as a chalcogenide-based or transition metal oxide, that switches between high and low resistance states based on applied voltage, allowing for efficient programming, erasing, and reading operations while maintaining low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the tunneling insulation layer is increased, then the memory characteristics are improved, but the operating speed decreases and power consumption increases
Solution Approach 1:
The patent divides the single-layer tunneling insulation structure into multiple layers with different materials and thicknesses. The first tunneling insulation layer has a thickness of 5-15nm, while the second tunneling insulation layer has a thickness of 15-30nm, allowing each layer to contribute differently to memory characteristics and operating speed
Solution Approach 2:
The patent uses composite material structures including polysilicon-oxide-nitride-oxide-silicon (SONOS) and polysilicon-oxide-nitride-oxide-silicon-oxide (SONOSONOS) configurations, combining multiple insulating materials to achieve both good memory characteristics and fast operating speed
2Speed
If the thickness of the tunneling insulation layer is reduced to improve operating speed, then the operating speed increases, but direct tunneling phenomenon and stress induced leakage current increase
Solution Approach 1:
The patent segments the tunneling insulation into two distinct layers with the first layer (5-15nm) optimized for tunneling control and the second layer (15-30nm) optimized for leakage prevention, allowing each segment to address specific aspects of the contradiction
Solution Approach 2:
Different regions of the tunneling insulation structure are assigned different material compositions and thicknesses - the first layer uses specific materials optimized for electron tunneling control while the second layer uses materials optimized for blocking leakage current, giving each local region specialized properties
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables faster operation with lower voltage requirements compared to traditional inverter technologies, integrating memory and logic functions effectively and reducing power consumption, thus addressing the limitations of existing non-volatile memory devices.
Implementation Method 1
a first switching layer (311) and a second switching layer (312) respectively include P-N diodes
Implementation Method 2
a first switching layer (311) and a second switching layer (312) respectively include P-N diodes
Data Source
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AI summary
Disclosed is a non-volatile inverter configured to perform a memory function. The non-volatile inverter (100) includes first and second transistors. The first transistor (TR1) includes a first gate electrode (GE1), a first electrode (E1, D1), and a second electrode (E2, S1). The second transistor (TR2) includes a second gate electrode (GE2) and a third electrode (E3, S2) and shares the second electrode (E2, D2) with the first transistor. The first transistor includes a first switching layer (110) and a first charge trap layer (TL). The first switching layer is configured to switch between a high resistance state and a low resistance state. The charge trap layer is configured to trap or de-trap charges according to the resistance state of the first switching layer. The first switching layer may include a P-N diode. The second transistor may include a second gate switching layer and a second charge trap layer.