Non-volatile Latch Using Capacitor Charge Traps
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Solution Overview
Problem
Existing non-volatile storage devices in semiconductor integrated circuits are complex, costly, and consume significant power due to the need for multiple material layers and complex programming/erasing processes, as well as large power consumption and complex reference circuits.
Innovation Solution
A non-volatile latch design utilizing N-channel MOS transistors and capacitors with capacitance ratios to achieve electron tunneling for data storage, allowing for a floating gate mechanism without additional processing complexity, and using a conventional CMOS process to reduce manufacturing costs and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If floating gate transistor with multiple material layers is used, then non-volatile storage capability is achieved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts the floating gate functionality from the complex multi-layer floating gate transistor structure and implements it using a simpler charge trap layer in a trench isolation structure. This maintains non-volatile storage capability while eliminating the need for multiple polysilicon layers and complex processing steps.
Solution Approach 2:
The patent changes the physical structure parameters by transitioning from a planar floating gate transistor to a vertical trench isolation structure with a charge trap layer. This structural parameter change simplifies the device architecture while preserving the non-volatile storage function.
2Reliability
If conventional non-volatile storage devices are used, then data storage is achieved, but power consumption increases
Solution Approach 1:
The charge trap layer in the trench isolation structure passively retains charge without requiring continuous power supply or complex refresh circuits. The device leverages the natural charge trapping capability of the oxide layer to maintain data, reducing active power consumption while ensuring data retention.
3Reliability
If floating gate transistor structure is used, then non-volatile storage is achieved, but manufacturing cost increases
Solution Approach 1:
The trench isolation structure with charge trap layer serves multiple functions: it provides electrical isolation between devices and simultaneously acts as the non-volatile storage element. This multi-functionality eliminates the need for separate floating gate structures, reducing manufacturing steps and costs while achieving non-volatile storage.
4Reliability
If complex reference circuit is used, then reliable sensing is achieved, but circuit area increases
Solution Approach 1:
The patent extracts the charge storage function from complex transistor structures and implements it in the trench isolation region, which naturally provides electrical isolation. This eliminates the need for complex reference circuits to sense device states, as the charge trapped in the isolation structure can be directly sensed with simpler circuitry, reducing overall circuit area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design simplifies the storage cell layout, reduces power consumption, and maintains data integrity even when power is removed, enabling efficient and cost-effective non-volatile storage without specialized processing steps.
Implementation Method 1
A first capacitor (18, 20, 22, 24) has a first electrode connected to a respective one of nodes 32, 34 and a second electrode connected to a gate of a transistor
Implementation Method 2
A non-volatile latch design utilizing N-channel MOS transistors and capacitors with capacitance ratios to achieve electron tunneling for data storage, allowing for a floating gate mechanism without additional processing complexity
Data Source
AI summary
A semiconductor storage device floats the gate of a conventional transistor between two capacitors to store a logic state which can be utilized to store the condition of a circuit such as a latching type circuit such as a flip-flop or register prior to a power down operation to save power. The gate and first terminals of the two capacitors preferably share the same conductive line such as a polysilicon segment. A second transistor and a second set of capacitors store the complementary state of the logic state so that complementary signals are provided for detecting the stored logic state. After the time for power down has ended, the state of the semiconductor storage device made up of the two transistors and four capacitors is sensed, and the detected logic state is loaded back into the latching type circuit.