Nonvolatile Logic Array Backup for Zero-Leakage SoC Sleep
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Solution Overview
Problem
Existing portable electronic devices face challenges in reducing leakage current during standby power mode, requiring continuous power to retain state information, which is inefficient for battery-operated devices and energy harvesting applications.
Innovation Solution
Implementing non-volatile logic (NVL) within System on Chip (SoC) using ferroelectric random access memory (FRAM) to store state information, allowing complete power removal without data loss, with NVL arrays dispersed throughout the logic cloud and controlled by a central NVL controller for efficient state backup and restoration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shadow latch is used to retain state information during standby power mode, then data retention is achieved, but leakage current is reduced only partially and continuous power is still required
Solution Approach 1:
The patent extracts the state retention function from the traditional shadow latch circuit and relocates it to a separate non-volatile memory array. This allows the main logic circuit to be completely powered down while the state information is stored externally in the non-volatile memory, achieving zero leakage current while maintaining data retention capability.
Solution Approach 2:
The patent introduces a non-volatile memory array as an intermediary between the logic circuit and the power supply. This intermediary stores the state information when power is removed and restores it when power is applied, enabling the logic circuit to enter complete standby mode without continuous power consumption while preserving state information.
2Loss of energy
If thick gate oxide transistors and high threshold voltage transistors are used in shadow latch, then leakage current is reduced, but device complexity and area overhead increase
Solution Approach 1:
The patent removes the complex shadow latch circuit entirely from the logic block and places the retention function in a separate non-volatile memory array. This extraction eliminates the need for thick gate oxide transistors, high threshold voltage transistors, and associated control logic, thereby reducing device complexity and area overhead while achieving the same leakage reduction goal.
3Speed
If state information is retained in shadow latch during standby mode, then rapid restoration is achieved, but power consumption during standby is not minimized
Solution Approach 1:
The patent uses a non-volatile memory array that can be rapidly programmed with state information and then left in a static, power-free state during standby. The memory array acts as a disposable storage medium that requires no continuous power to maintain data, enabling both rapid restoration and minimal standby power consumption.
Solution Approach 2:
The patent performs the state retention action in advance by storing state information in the non-volatile memory array before power is removed. This preliminary storage action ensures that when power is restored, the state information is already available for immediate restoration without requiring continuous power during the standby period.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables zero leakage in sleep mode and rapid system state restoration, reducing energy consumption and eliminating the need for continuous power, making it suitable for energy harvesting applications and devices with limited battery capacity.
Implementation Method 1
Implementing non-volatile logic (NVL) within System on Chip (SoC) using ferroelectric random access memory (FRAM) to store state information
Data Source
AI summary
A processing device is operated using a plurality of volatile storage elements. N groups of M volatile storage elements of the plurality of volatile storage elements per group are connected to an N by M size non-volatile logic element array of a plurality of non-volatile logic element arrays using a multiplexer. The multiplexer connects one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time. A corresponding non-volatile logic controller controls the multiplexer operation with respect to the connections between volatile storage elements and non-volatile storage elements.