Nonvolatile Logic Array Restore for Low-Leakage Wake-Up
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Solution Overview
Problem
Existing portable electronic devices face challenges in reducing leakage current during standby power mode, requiring continuous power to retain state information, which is inefficient for battery-operated devices and energy harvesting applications.
Innovation Solution
The implementation of non-volatile logic (NVL) in System on Chip (SoC) using ferroelectric random access memory (FRAM) allows for zero leakage during sleep mode and rapid system state restoration upon power-up, eliminating the need for continuous power to retain flip-flop states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shadow latch is used to retain state information during standby power mode, then data retention is achieved, but leakage current is reduced only partially and continuous power is still required
Solution Approach 1:
The patent changes the fundamental parameter of state retention from volatile (shadow latch requiring continuous power) to non-volatile (FRAM). By using ferroelectric random access memory with zero leakage characteristics, the system achieves complete power shutdown capability while maintaining data retention, eliminating the trade-off between reliability and energy loss.
2Reliability
If continuous power is provided to shadow latch for data retention, then state information is preserved, but energy consumption increases
Solution Approach 1:
The patent extracts the power consumption burden from the state retention function. By separating the volatile logic circuitry from the non-volatile FRAM memory, the system can completely power down the logic portion while FRAM maintains state information without any power, thereby eliminating continuous power consumption for retention purposes.
Solution Approach 2:
The invention changes the retention mechanism from active (requiring continuous power supply to shadow latch) to passive (FRAM maintaining state without power). This parameter change from volatile to non-volatile storage eliminates the energy consumption issue entirely while preserving state information.
3Reliability
If system state is restored from shadow latch upon power-up, then functionality is resumed, but boot time is extended
Solution Approach 1:
The patent applies preliminary action by maintaining system state in FRAM during power-down periods. When power is restored, the state is already prepared and available in non-volatile memory, eliminating the need for lengthy initialization sequences and significantly reducing boot time while ensuring complete functionality restoration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables portable devices to maintain functionality without power loss, reducing energy consumption and boot time, making them suitable for energy harvesting applications and improving battery life.
Implementation Method 1
The plurality of non-volatile logic elements may include ferroelectric random access memory (FRAM)
Data Source
AI summary
Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.