Nonvolatile Logic Array Backup for Fast Wake-Up and Zero Leakage
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Solution Overview
Problem
Existing portable electronic devices face challenges in reducing leakage current during standby power mode, requiring continuous power to retain state information, which is inefficient for battery-operated devices and energy harvesting applications.
Innovation Solution
Implementing non-volatile logic (NVL) elements, such as ferroelectric random access memory (FRAM), which allows complete power removal without losing state information, enabling instant-on capabilities and reducing energy consumption by using multiple power domains and NVL arrays to manage state retention and restoration efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shadow latch is used to retain state information during standby power mode, then data retention is improved, but leakage current is reduced only partially and additional power supply circuitry is required
Solution Approach 1:
The patent extracts the state retention function from the traditional shadow latch circuit and relocates it to a separate non-volatile memory array. This allows the main logic circuit to be completely powered down without requiring any retention circuitry to remain active, eliminating both leakage current and the need for separate always-on power supplies.
Solution Approach 2:
The patent introduces a non-volatile memory array as an intermediary between the logic circuit and state retention. This intermediary stores state information when power is removed and restores it when power is reapplied, enabling complete power removal while maintaining data retention capability.
2Loss of energy
If multi-threshold CMOS technology is used to reduce leakage current, then power consumption is improved, but device complexity increases due to multiple threshold voltage transistors
Solution Approach 1:
The patent removes the complexity of multi-threshold CMOS circuits by extracting the power management function to a controller that selectively powers down circuit blocks. This allows standard CMOS transistors to be used without requiring complex multi-threshold voltage transistor designs, simplifying the device structure while achieving low power consumption.
3Loss of energy
If complete logic circuit is powered down to eliminate leakage current, then energy consumption is improved, but state information is lost and system must reboot
Solution Approach 1:
The patent performs preliminary action by saving state information to a non-volatile memory array before powering down the logic circuit. This preliminary storage action ensures that when power is removed, the state information is already preserved and can be quickly restored without rebooting the system.
Solution Approach 2:
The patent creates a copy of the state information in a non-volatile memory array before powering down the main logic circuit. This copying mechanism allows the original circuit to be completely powered off while a duplicate copy of the state persists in the non-volatile memory, preventing information loss.
4Speed
If traditional volatile memory is used for state retention, then access speed is improved, but continuous power is required causing battery life reduction
Solution Approach 1:
The patent segments the memory system into two distinct parts: a volatile memory array for fast state access during active operation, and a non-volatile memory array for state retention during power-off periods. This segmentation allows each part to optimize for its specific function - speed during operation and energy savings during standby - resolving the contradiction between access speed and battery life.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables zero-leakage operation in sleep mode, rapid system state restoration, and reduced energy consumption, making it suitable for energy harvesting applications and extending battery life in portable devices.
Implementation Method 1
Each bit cell includes two capacitors, e.g., ferroelectric capacitors
Data Source
AI summary
Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.