Non-Volatile Logic Latch Design to Minimize Memory Writes
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Solution Overview
Problem
Next-generation memory devices with high storage capacity and low power consumption are needed, and existing non-volatile memory cells have limited endurance for write operations, affecting the reliability of logic circuits.
Innovation Solution
A non-volatile logic circuit design that includes a latch unit with a pair of latch nodes and non-volatile memory cells, where write operations are performed only when a write enable signal is activated, and data is read using a read enable signal, reducing the number of write operations and enhancing endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If non-volatile memory cells are used to store data in logic circuits, then data retention without power is improved, but the endurance for write operations deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-storing boot data in non-volatile memory cells before the system needs to boot. This allows the system to quickly retrieve and execute boot instructions without performing write operations during the boot process, thereby preserving the limited write endurance of the non-volatile memory cells while maintaining their data retention advantage.
Solution Approach 2:
The patent segments the memory system into two parts: non-volatile memory cells for storing boot data and volatile memory for storing frequently accessed data and instructions. This segmentation allows the system to leverage the data retention capability of non-volatile memory for critical boot information while using volatile memory for operations that require frequent writing, thus protecting the endurance of non-volatile memory cells.
2Productivity
If write operations are performed frequently on non-volatile memory cells, then data updates are improved, but the lifespan of memory cells deteriorates
Solution Approach 1:
The patent performs write operations in advance by pre-loading boot data into non-volatile memory cells during manufacturing or initial setup. This preliminary action eliminates the need for frequent write operations during normal operation and boot processes, thereby extending the lifespan of memory cells while ensuring rapid data availability when needed.
3Loss of time
If non-volatile memory cells are used instead of external ROM, then booting time is reduced, but device complexity increases
Solution Approach 1:
The patent merges the ROM functionality directly into the logic circuit by integrating non-volatile memory cells within the circuit architecture. This consolidation eliminates the need for separate external ROM components and their associated interface circuits, thereby reducing booting time through faster data access while actually simplifying the overall device structure by removing external components.
Data Source
AI summary
Provided is a non-volatile logic circuit that includes a latch unit having a pair of latch nodes and a pair of non-volatile memory cells to be supplied first and second write voltages according to data of the pair of latch nodes when a write enable signal is activated such that a write operation is performed with respect to the pair of non-volatile memory cells. The first and second write voltages are different and logic values of data written to the respective non-volatile memory cells are different.