Nonvolatile Logic Array Power Segmentation for Zero-Leakage Standby
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Solution Overview
Problem
Existing portable electronic devices face challenges in reducing leakage current during standby power mode, requiring continuous power to retain state information, which is inefficient for battery-operated devices and energy harvesting applications.
Innovation Solution
Implementing non-volatile logic (NVL) elements, such as ferroelectric random access memory (FRAM), which allows state retention without power and enables instant-on capabilities, using a system on a chip (SoC) with multiple power domains and NVL arrays to manage state storage and retrieval efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional volatile logic circuits are used with shadow latches for state retention, then state information can be retained during standby power mode, but leakage current is still generated and continuous power is required
Solution Approach 1:
The logic circuit is divided into multiple power domains (first power domain and second power domain) that can be independently controlled. The first power domain contains logic circuits that can be powered down during standby, while the second power domain contains retention circuits that maintain state information with minimal power consumption, eliminating the need for a continuously powered shadow latch.
Solution Approach 2:
The patent changes the operational parameters of the logic circuits by switching between different power domains with different voltage levels. During active mode, the first power domain operates at full voltage for high-performance logic operations. During standby mode, the first power domain is powered down and the second power domain operates at reduced voltage to maintain state with minimal leakage current.
2Loss of energy
If power is turned off during standby power mode to conserve energy, then energy consumption is reduced, but system state cannot be retained and reset is required
Solution Approach 1:
The system is segmented into first power domain logic circuits and second power domain retention circuits. During standby mode, the first power domain is completely powered off to eliminate energy consumption, while the second power domain remains active at reduced power to retain system state information, enabling instant-on capability without full system reset.
Solution Approach 2:
The retention circuits in the second power domain preliminarily preserve the system state before complete power-down of the first power domain. This preliminary state preservation allows the system to be quickly restored without requiring a full reset sequence, reducing both energy consumption and wake-up time.
3Loss of energy
If shadow latch is detached from the rest of the circuit during normal operation to reduce leakage, then leakage current is reduced, but system performance is degraded
Solution Approach 1:
The circuit is segmented into first power domain logic circuits for high-performance operation and second power domain retention circuits for low-power state maintenance. During normal operation, both power domains are active with the first power domain providing full performance while the second power domain maintains state information, eliminating the need to detach retention circuits and maintaining optimal system performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables zero leakage in sleep mode and rapid system state restoration, reducing energy consumption and eliminating the need for system resets, making it suitable for energy harvesting applications and handheld devices with limited power resources.
Implementation Method 1
Implementing non-volatile logic (NVL) elements, such as ferroelectric random access memory (FRAM), which allows state retention without power
Data Source
AI summary
A computing device includes a first set of non-volatile logic element arrays associated with a first function and a second set of non-volatile logic element arrays associated with a second function. The first and second sets of non-volatile logic element arrays are independently controllable. A first power domain supplies power to switched logic elements of the computing device, a second power domain supplies power to logic elements configured to control signals for storing data to or reading data from non-volatile logic element arrays, and a third power domain supplies power for the non-volatile logic element arrays. The different power domains are independently powered up or down based on a system state to reduce power lost to excess logic switching and the accompanying parasitic power consumption during the recovery of system state and to reduce power leakage to backup storage elements during regular operation of the computing device.