Nonvolatile Logic Array Backup for Zero-Leakage State Restore
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Solution Overview
Problem
Existing portable electronic devices face challenges in reducing leakage current during standby power mode, requiring continuous power to retain state information, which is inefficient for battery-operated devices and energy harvesting applications.
Innovation Solution
Implementing non-volatile logic (NVL) within System on Chip (SoC) using ferroelectric random access memory (FRAM) to store state information, allowing complete power removal without data loss, with NVL arrays dispersed throughout the logic cloud and controlled by a central NVL controller for efficient power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shadow latch is used to retain state information during standby power mode, then data retention is improved, but leakage current is reduced only partially and some power is still required
Solution Approach 1:
The patent extracts the state retention function from the traditional shadow latch circuit and relocates it to a separate non-volatile memory element. This allows the main logic circuit to be completely powered down while the extracted state information is preserved in the non-volatile memory without requiring any standby power.
Solution Approach 2:
The patent introduces a non-volatile memory element as an intermediary between the logic circuit and state retention. This intermediary stores the state information when power is removed and restores it when power is reapplied, eliminating the need for continuous power to maintain state.
2Productivity
If continuous power is provided to logic circuits, then system performance is maintained, but energy consumption increases for battery-operated devices
Solution Approach 1:
The patent performs preliminary action by storing the complete system state in non-volatile memory before power is removed. This allows the system to be completely powered down to conserve energy, with the pre-stored state ready for rapid restoration when power is reapplied, thus eliminating energy consumption during standby while maintaining the ability to resume performance quickly.
3Loss of energy
If power is completely removed from logic circuits, then energy consumption is minimized, but state information is lost
Solution Approach 1:
The patent extracts state information from the volatile logic circuits and stores it in non-volatile memory elements before power is completely removed. This extraction allows the logic circuits to be fully powered down for minimal energy consumption while the extracted state information is safely preserved in the non-volatile storage.
Solution Approach 2:
The patent creates a copy of the system state in non-volatile memory elements. This copy serves as a backup that persists when power is removed, allowing the original volatile state to be discarded along with the power, and the copy to be restored later without information loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables zero leakage in sleep mode and rapid system state restoration upon power-up, reducing energy consumption and eliminating the need for constant power sources, ideal for energy harvesting applications and handheld devices with limited resources.
Implementation Method 1
Implementing non-volatile logic (NVL) within System on Chip (SoC) using ferroelectric random access memory (FRAM) to store state information
Data Source
AI summary
Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.