Nonvolatile Logic Switch Layout for Selective Memory Writing
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Solution Overview
Problem
Conventional programmable logic switches in FPGAs using SRAM face issues such as data loss upon power shutdown, increased chip area due to SRAM cells, and reduced operation speed due to voltage transmission time, along with the need for multiple power sources and thick gate insulating films for high erase voltages, which complicates memory cell operation.
Innovation Solution
A programmable logic switch design incorporating two nonvolatile memory transistors and a pass transistor, where selective writing is achieved using channel hot electrons and controlled voltages to prevent gate destruction, allowing for high-speed operation without additional devices and minimizing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SRAM is used for programmable logic switches, then operation speed is maintained, but data is lost when power is shut off and chip area increases
Solution Approach 1:
The patent changes the memory type from volatile SRAM to nonvolatile memory, fundamentally altering the data retention parameter. This allows data to be preserved without power, eliminating the need for large SRAM cells while maintaining logic switch functionality.
Solution Approach 2:
The patent extracts the need for additional read memory areas by using nonvolatile memory that inherently retains data. This eliminates the requirement for separate memory structures, reducing overall chip area while maintaining data retention capability.
2Reliability
If nonvolatile flash memory is used, then data retention is improved, but operation speed decreases due to voltage transmission time
Solution Approach 1:
The patent segments the memory cell structure into two separate nonvolatile memory devices connected in series, with their gates connected to a common control line. This segmentation allows independent control and reduces the capacitive load on the control gate, improving switching speed while maintaining data retention.
Solution Approach 2:
The patent implements dynamic voltage control where different voltages are applied to the sources of the two nonvolatile memory devices during operation mode versus programming/erasing mode. This dynamic voltage adjustment optimizes both operation speed and data retention by reducing voltage transmission time during normal operation.
3Reliability
If high erase voltage is applied to nonvolatile memory, then data erasing is effective, but gate insulating film must be made thick which reduces operation speed
Solution Approach 1:
The patent applies different voltage conditions to different parts of the memory cell structure. During erasing, high voltage is localized to the drain of the nonvolatile memory device being erased, while the gate insulating film is protected by applying 0V to its substrate. This localized voltage application enables effective erasing without requiring a thick gate insulating film, thus maintaining high operation speed.
4Reliability
If additional devices are added to prevent gate destruction, then reliability is improved, but device complexity and chip area increase
Solution Approach 1:
The patent makes the existing control structure multi-functional by applying different voltage levels to the same control gate and substrate connections depending on the operation mode. The control gate serves both for normal operation and for protecting against gate destruction during high-voltage erasing, eliminating the need for additional protective devices while improving reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables selective and efficient writing to memory transistors while preventing gate destruction, reducing chip area and power source requirements, and maintaining high-speed operation by using controlled voltages and channel hot electrons, thus addressing the limitations of conventional SRAM-based switches.
Implementation Method 1
a first charge storage film formed on the first insulating film; a second insulating film formed on the first charge storage film
Implementation Method 2
selective writing is achieved using channel hot electrons
Data Source
AI summary
One embodiment provides a programmable logic switch in which a first nonvolatile memory and a second nonvolatile memory are formed in the same well, and in which to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage is applied to a first line connected with gate electrodes of the first and second nonvolatile memories, a second write voltage is applied to a second line connected to a source in the first nonvolatile memory, and a third write voltage lower than the second write voltage is applied to a fourth line connected to a source of the second nonvolatile memory.