Nonvolatile MCU Architecture With MRAM for Low-Power Signal Processing
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Solution Overview
Problem
Existing microcontroller units (MCUs) with low power consumption and high performance are not suitable for sensor nodes that process large numbers of signals and extract efficient information, as they fail to suppress data amount transferred to data centers.
Innovation Solution
A device comprising a Magnetic RAM (MRAM) with multiple memory cells, a nonvolatile CPU, a nonvolatile FPGA-ACC, and a power-gating controller, which enables efficient data transfer and processing by using nonvolatile memory cells and power-gating to reduce power consumption and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional MCUs with low power consumption are used, then power consumption is reduced, but processing performance for large numbers of signals deteriorates
Solution Approach 1:
The system is divided into two processing paths: a high-speed path using NV-FPGA-ACC for signal processing and a low-power path using NV-CPU for control operations. This segmentation allows each component to operate in its optimal performance range, with the FPGA handling computationally intensive signal processing tasks while the CPU manages system control, thereby achieving both high processing capability and low power consumption.
Solution Approach 2:
The MRAM serves as an intermediary between the NV-CPU and NV-FPGA-ACC, providing high-speed data transfer capability. The access controller acts as another intermediary, managing data flow between components and implementing intelligent data transfer strategies that reduce overall system power consumption while maintaining high processing throughput.
2Loss of information
If data is transferred to data center for processing, then information extraction capability is improved, but data transfer amount and power consumption increase
Solution Approach 1:
The NV-FPGA-ACC performs preliminary signal processing and feature extraction locally at the sensor node before data leaves the device. By preprocessing signals and extracting relevant features on-site, the system reduces the amount of raw data that needs to be transferred to external data centers, thereby decreasing data transfer power consumption while maintaining information extraction efficiency.
3Use of energy by moving object
If nonvolatile memory is used in MCU, then power consumption is reduced, but processing speed for large data amounts deteriorates
Solution Approach 1:
The system merges nonvolatile memory (MRAM) with high-speed processing units (NV-FPGA-ACC and NV-CPU) to create a unified architecture that combines the power-saving benefits of nonvolatile storage with the processing speed of volatile memory systems. The MRAM provides both storage and fast access capability, eliminating the traditional trade-off between power consumption and processing speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves low power consumption and high performance by eliminating the need for data backup and using a reconfigurable FPGA-ACC for high-speed signal processing, allowing effective data transfer and operation at high speeds.
Implementation Method 1
a power-gating controller that controls power supply to each memory cell in the MRAM, the nonvolatile CPU, and the nonvolatile FPGA-ACC
Implementation Method 2
an MRAM configured to include multiple memory cells separated into multiple regions including selection transistors and MTJs
Data Source
AI summary
The present invention provides a device with low power and high performance, which can be applied to sensor nodes, a sensor node using the same, an access controller, a data transfer method, and execute a processing method in a microcontroller. The device has: an MRAM; a non-volatile CPU configured to include a nonvolatile memory; a non-volatile FPGA-ACC configured to include a nonvolatile memory and execute a part of operations on the nonvolatile CPU; and a power-gating control unit that controls power supply to each memory cell in the MRAM, the non-volatile CPU, and the non-volatile FPGA-ACC. The device is further provided with an access controller that controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.