Nonvolatile Memory Device with 3D Stacked Structure
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Solution Overview
Problem
As semiconductor devices integrate finer circuit patterns, there is a need for improved dimensional and positional accuracy, and nonvolatile memory devices with three-dimensionally stacked structures require higher reliability to retain charge in smaller memory cell regions effectively.
Innovation Solution
A nonvolatile memory device with a cross-point type structure, featuring a memory cell array with global and local bit lines, word lines, a selector, a current limitation layer, a metal ion source layer, and a resistance change layer, where the resistance change layer transitions between states based on applied voltage, allowing for data storage and erasure through controlled filament formation and dissolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the integration degree is increased by using a three-dimensionally stacked structure, then the memory capacity and integration density are improved, but the reliability and charge retention capability deteriorate due to the smaller cell region size
Solution Approach 1:
The patent transitions from a two-dimensional memory cell structure to a three-dimensionally stacked structure by vertically stacking multiple memory cell layers. Each layer includes bit lines, word lines, and resistance change layers arranged in the vertical direction, thereby increasing integration density while maintaining functional performance through spatial optimization
Solution Approach 2:
The patent introduces a current limitation layer with specific resistance characteristics positioned between the bit line and the resistance change layer. This layer provides localized current control to prevent excessive current flow, thereby protecting the resistance change layer and improving charge retention capability in the smaller cell regions of the three-dimensional structure
2Productivity
If the line width is reduced to make the pattern finer, then the integration degree is improved, but the dimensional accuracy and positional accuracy deteriorate
Solution Approach 1:
The patent utilizes vertical stacking to achieve higher integration density without further reducing the lateral dimensions of the memory cell patterns. By extending the structure in the vertical direction, it maintains manufacturing feasibility while increasing capacity
Solution Approach 2:
The patent employs a composite structure consisting of multiple functional layers including the resistance change layer, current limitation layer, metal ion source layer, and insulating layers. This composite approach allows each layer to be optimized independently for its specific function, maintaining manufacturing precision while achieving fine integration
3Reliability
If a current limitation layer and metal ion source layer are added between the bit line and resistance change layer, then the reliability is improved through controlled filament formation, but the device complexity increases
Solution Approach 1:
The patent introduces a current limitation layer as an intermediary between the bit line and the resistance change layer. This layer controls the current flow to enable reliable filament formation and dissolution in the resistance change layer, thereby improving data storage reliability through controlled electrical characteristics
Solution Approach 2:
The patent introduces a metal ion source layer as an intermediary that supplies metal ions to the resistance change layer for filament formation. This layer ensures controlled and reproducible resistance changes, improving reliability while the entire multi-layer structure is manufactured using standard semiconductor fabrication processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the integration density and reliability of nonvolatile memory devices by enabling precise control over resistance changes, ensuring reliable data storage and scalability in smaller cell sizes.
Implementation Method 1
a resistance change layer provided between the current limitation layer and the third interconnections
Implementation Method 2
allowing for data storage and erasure through controlled filament formation and dissolution
Implementation Method 3
a metal ion source layer provided between the current limitation layer and the third interconnections
Data Source
AI summary
A nonvolatile memory device includes: a first interconnection extending in a first direction; a second interconnection extending in a second direction, and a lower end of the second interconnection being located above the first interconnection; a plurality of third interconnections extending in a third direction, and the third interconnections being arranged in the second direction; a current limitation layer provided between the second interconnection and the third interconnections; a metal ion source layer provided between the current limitation layer and the third interconnections; a resistance change layer provided between the current limitation layer and the third interconnections; and a selector provided between the first interconnection and the lower end of the second interconnection.