Nonvolatile Memory Chip Address Initialization Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing number of nonvolatile memory chips in a multi-chip package leads to an increase in the size of the chip due to the need for additional pads for chip address allocation, which complicates routing and increases the chip size significantly.
Innovation Solution
A nonvolatile memory device with a chip address initialization circuit that receives and stores chip addresses, generates next chip addresses, and outputs them through enable signals, allowing for efficient allocation of chip addresses without the need for additional pads, thereby minimizing the chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional pads are added for chip address allocation in multi-chip packages, then the ability to recognize multiple nonvolatile memories independently is improved, but the chip size increases significantly
Solution Approach 1:
The patent combines the chip address input function with the existing input/output pads that are already used for data transmission. Instead of adding separate dedicated pads for chip addresses, the system reuses the data pads for dual purposes: transmitting data during normal operations and transmitting chip addresses during initialization. This merging eliminates the need for additional pads while maintaining the ability to independently recognize multiple nonvolatile memories in a multi-chip package.
Solution Approach 2:
The input/output pads are designed to perform multiple functions: they serve as data transmission channels during normal memory operations and as chip address input channels during the initialization phase. The chip address initialization circuit enables this multi-functionality by controlling when these pads are used for address input versus data transmission, allowing the same physical infrastructure to support both address allocation and data I/O without requiring separate dedicated pads.
2Adaptability or versatility
If additional pads are added for chip address allocation, then chip address assignment capability is improved, but the routing complexity increases
Solution Approach 1:
The patent merges the chip address routing with the existing data bus infrastructure. The same physical pads and routing paths that carry data between the memory chips and the memory controller are reused to carry chip addresses during the initialization phase. This eliminates the need for separate dedicated routing paths for address signals, thereby reducing routing complexity while maintaining full chip address assignment capability for multiple nonvolatile memories.
Solution Approach 2:
The chip address initialization circuit performs address assignment during the initialization phase before normal data operations begin. By establishing the chip address mappings upfront through the existing data pads, the system avoids the need for complex continuous address routing during data operations. The initialization process sets up the address-to-chip mapping once, and this configuration is maintained during subsequent data transmissions, simplifying the overall routing requirements.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Disclosed is a nonvolatile memory, which includes a plurality of input/output pads connectable to a plurality of data lines, an enable input pad, an enable output pad, and a chip address initialization circuit. The chip address initialization circuit receives a current chip address through the plurality of input/output pads, stores the current chip address in response to a current enable signal received through the enable input pad, outputs a next enable signal through the enable output pad, and outputs a next chip address through the plurality of input/output pads.