Non-volatile Memory Address Tables for Command Queue Blockage
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Solution Overview
Problem
Existing non-volatile memory systems often experience blockages in host commands due to asymmetrical workloads or maintenance operations, where slower memory banks can lead to full command queues and restricted queue depths, preventing commands from being sent to idle banks.
Innovation Solution
A non-volatile memory system with a memory die command manager and a command manager that dynamically assigns physical block addresses to virtual logical block addresses, allowing data storage at any available die independent of host logical block addresses, using two address tables to manage these associations and prevent command accumulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If logical block addresses are mapped exclusively to a subset of physical address space (bank), then data storage organization is simplified, but host command queues become blocked when the designated bank is slow or full
Solution Approach 1:
The patent divides the address mapping function into two separate tables: a first address table that maps physical block addresses to virtual logical block addresses, and a second address table that maps virtual logical block addresses to host logical block addresses. This segmentation allows the system to decouple the physical storage organization from the host interface, enabling commands to be routed to any available bank rather than being constrained to a single designated bank, thereby preventing command queue blockages.
Solution Approach 2:
The patent introduces virtual logical block addresses as an intermediary layer between host logical block addresses and physical block addresses. This intermediary abstraction allows the system to translate host commands through multiple mapping stages, enabling flexible routing of commands to any available memory bank while maintaining the simplicity of host interface operations. The virtual address layer acts as a buffer that decouples host operations from physical bank status.
2Reliability
If host command queues are restricted to a maximum queue depth, then protocol compliance is maintained, but commands to idle banks are blocked when queues are full
Solution Approach 1:
The patent implements dynamic command routing where the system continuously monitors the status of different memory banks and dynamically selects which bank to use for each command based on current availability. The command manager can redirect commands from full or slow banks to idle banks, and the address tables are dynamically updated to reflect current bank status. This dynamic adaptation allows the system to maintain protocol-compliant queue depths while maximizing command acceptance by utilizing all available banks.
3Ease of operation
If data is stored in specific memory banks based on host logical block addresses, then address mapping is straightforward, but access latency increases when designated banks are slow or under maintenance
Solution Approach 1:
The patent segments the address mapping into two independent tables that can be managed separately. The first table maps physical addresses to virtual logical addresses, and the second table maps virtual logical addresses to host logical addresses. This segmentation allows the system to update physical mappings without affecting host interface operations, enabling seamless bank switching and load balancing to minimize access latency while maintaining mapping simplicity.
Solution Approach 2:
The patent changes the parameter space by introducing virtual logical block addresses as an intermediate parameter layer. Instead of directly mapping host logical block addresses to physical block addresses, the system uses virtual addresses as a flexible parameter that can be remapped to different physical banks based on current performance characteristics, maintenance status, or load conditions. This parameter transformation enables dynamic optimization of access latency without complicating the host interface.
Data Source
AI summary
Non-volatile memory systems utilizing storage address tables are disclosed. A non-volatile memory system may include a non-volatile memory, a memory die command manager in communication with the memory, and a command manager in communication with the memory die command manager. The memory die command manager is configured to identify a free die of the memory to store data, where the free die of the memory is identified independent of a host logical block address associated with the data; store the data at a physical block address at the free die; and generate an entry in a first address table, the first address table associating the physical block address with a virtual logical block address. The command manager is configured to generate an entry in a second address table, the second address table associating the virtual logical block address with a host logical block address received with the host write command.