Nonvolatile Memory Addressing with Logical-Physical Interface Selection
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Solution Overview
Problem
Conventional SSDs consume excessive memory resources and degrade I/O performance due to duplex address translation and application-level garbage collection, leading to increased data write amounts and reduced storage performance.
Innovation Solution
Implement a memory system with a controller that supports multiple interfaces for accessing NAND flash memory, allowing the host to designate logical addresses in some regions and physical addresses in others, with the controller managing physical address translation and garbage collection, thereby reducing the need for the host to handle NAND flash memory directly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If duplex address translation and application-level garbage collection are implemented in the host, then address management flexibility is improved, but memory resource consumption increases and I/O performance degrades
Solution Approach 1:
The patent segments the address translation and garbage collection functions between two levels: application-level (host) and media-level (storage device). The host performs application-level address translation and garbage collection for logical addresses, while the storage device performs media-level address translation and garbage collection for physical NAND flash addresses. This segmentation allows both levels to operate independently and efficiently, resolving the contradiction between address management flexibility and I/O performance.
Solution Approach 2:
The patent introduces a dual-layer address translation mechanism as an intermediary between the host and NAND flash memory. The first layer (application-level) translates host logical addresses to device logical addresses, and the second layer (media-level) translates device logical addresses to physical NAND flash addresses. This intermediary structure enables flexible address management at the host level while maintaining efficient I/O operations through automated media-level translation, preventing the performance degradation that would occur with direct host-level implementation.
2Measurement precision
If the host handles NAND flash memory directly with physical address designation, then control precision is improved, but device complexity and resource consumption increase
Solution Approach 1:
The patent segments the address management responsibility between two independent systems: the host manages application-level logical addresses with full precision control, while the storage device manages media-level physical addresses independently. This segmentation allows the host to maintain precise address control for data management purposes without directly handling physical NAND flash addresses, thereby reducing host system complexity while preserving address designation precision where needed.
Solution Approach 2:
The patent introduces device logical addresses as an intermediary layer between host logical addresses and physical NAND flash addresses. The host designates data using application-level logical addresses with full precision, and the storage device automatically handles the translation to physical addresses through its media-level address translation mechanism. This intermediary structure eliminates the need for the host to directly manage physical addresses, reducing host system complexity while maintaining precise address control at the application level.
3Adaptability or versatility
If application-level garbage collection is implemented, then data management flexibility is improved, but data write amount increases and storage performance reduces
Solution Approach 1:
The patent segments garbage collection into two independent levels: application-level garbage collection managed by the host and media-level garbage collection managed by the storage device. The host performs application-level garbage collection on logical addresses to maintain data management flexibility, while the storage device simultaneously performs media-level garbage collection on physical NAND flash blocks to minimize actual data writes. This segmentation allows both levels to optimize their operations independently, preventing the increase in total data write amount that would occur with single-level garbage collection while maintaining data management flexibility at the application level.
Solution Approach 2:
The patent introduces a dual-layer address translation and garbage collection system as an intermediary between the host and NAND flash memory. The application-level garbage collection at the host manages logical addresses flexibly, while the media-level garbage collection at the storage device manages physical blocks efficiently. This intermediary structure enables the host to perform flexible data management operations on logical addresses without directly triggering excessive physical writes to the NAND flash memory, as the media-level garbage collection independently optimizes physical write operations.
Data Source
AI summary
According to one embodiment, when a read request received from a host includes a first identifier indicative of a first region, a memory system obtains a logical address from the received read request, obtains a physical address corresponding to the obtained logical address from a logical-to-physical address translation table which manages mapping between logical addresses and physical addresses of the first region, and reads data from the first region, based on the obtained physical address. When the received read request includes a second identifier indicative of a second region, the memory system obtains physical address information from the read request, and reads data from the second region, based on the obtained physical address information.