Nonvolatile Memory Read Error Correction via Adjacent Cell Threshold Detection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Highly integrated NAND flash memory devices face errors during read operations due to excessive program threshold voltage increases in adjacent memory cells, which can prevent the formation of channels necessary for correct data reading, especially as device integration increases.

Innovation Solution

A nonvolatile memory device and method that include a latch unit for detecting threshold voltages of adjacent memory cells, a bit line coupling unit for electrical connection, and reset units to adjust read pass voltages dynamically during read operations, ensuring accurate data retrieval by comparing threshold voltages with a reference voltage and adjusting voltages accordingly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory cells are highly integrated with reduced spacing, then memory capacity is increased, but read operation errors increase due to excessive threshold voltage rise in adjacent cells

Engineering Contradiction:
Improvememory capacityVSAvoidread operation accuracy
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies preliminary action by detecting the threshold voltage of adjacent memory cells before performing the read operation on the selected memory cell. This allows the system to prepare appropriate read pass voltages in advance, ensuring that adjacent cells with excessively high threshold voltages will receive compensated voltages that enable proper channel formation, thereby preventing read errors before they occur.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements parameter changes by dynamically adjusting the read pass voltage applied to adjacent memory cells based on their detected threshold voltages. When an adjacent cell's threshold voltage is higher than a reference voltage, the system increases the read pass voltage for that specific cell to compensate for the excessive threshold rise, ensuring the channel can form properly during the read operation of the selected cell.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If read pass voltage is increased to ensure channel formation in adjacent cells, then read accuracy is improved, but power consumption increases

Engineering Contradiction:
Improveread operation accuracyVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies local quality by selectively adjusting the read pass voltage only for specific adjacent memory cells that have excessively high threshold voltages, rather than uniformly increasing the voltage for all adjacent cells. The system detects the threshold voltage of each adjacent cell individually and applies compensated voltage only where needed, thereby improving read accuracy for problematic cells while minimizing unnecessary power consumption in cells that do not require compensation.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8270221B2Nonvolatile memory device and method of operating the same
Publication Date: 2012.09.18 SK HYNIX INC
  • US8270221B2 patent drawing
  • US8270221B2 patent drawing
  • US8270221B2 patent drawing

AI summary

A nonvolatile memory device includes a cell string, including a drain select transistor coupled to a bit line, a source select transistor coupled to a common source line, and memory cells coupled in series between the drain select transistor and the source select transistor, a latch unit, including a first latch for storing a detection result of a threshold voltage of a second memory cell adjacent to a first memory cell selected from among the memory cells and a second latch for storing a detection result of a threshold voltage of the first memory cell, and a first reset unit electrically coupled between the first and second latches and configured to reset the second latch, during a time in which a read operation is performed on the first memory cell, in response to a first reset signal and the detection result stored in the first latch.