Nonvolatile Memory Array With Segmented Resistance Layers
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Solution Overview
Problem
Conventional nonvolatile memory element configurations face challenges in miniaturization and mass production, with issues related to resistance variable layer reliability, parasitic wire resistance, and cross-talk between adjacent electrodes, which affect retention characteristics and compatibility with semiconductor processes.
Innovation Solution
A nonvolatile memory element array using a multi-layer resistance layer structure with a high-resistance layer and a low-resistance layer, where the low-resistance layer is isolated from adjacent memory cells and connected only at specific surfaces of the high-resistance layer, allowing for proper resistance values and reduced leak currents, thereby enhancing retention characteristics and enabling miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a resistance variable layer is used as the memory portion material, then miniaturization and speed increase are expected, but resistance value stability and retention characteristics deteriorate
Solution Approach 1:
The resistance variable layer is divided into multiple segments (first resistance variable layer and second resistance variable layer) with different resistance characteristics. This segmentation allows each layer to contribute differently to the overall resistance change, improving stability while maintaining miniaturization benefits.
Solution Approach 2:
Different regions of the resistance variable layer structure are assigned different resistance properties. The first resistance variable layer has higher resistance while the second has lower resistance, creating local quality variations that stabilize the overall resistance characteristics during miniaturization.
2Ease of manufacture
If the resistance variable layer structure is simplified for mass production, then manufacturing ease improves, but retention characteristics and reliability worsen
Solution Approach 1:
The resistance variable layer is segmented into multiple layers that can be formed using standard semiconductor manufacturing processes. This segmentation maintains compatibility with mass production techniques while the multi-layer structure itself improves retention characteristics through distributed resistance control.
Solution Approach 2:
The multi-layer resistance variable layer structure serves multiple functions simultaneously: it provides the necessary resistance change for memory operation, ensures stable retention characteristics, and remains compatible with existing semiconductor manufacturing processes, achieving universality across different requirements.
3Device complexity
If conventional resistance variable layer structures are used, then device complexity is reduced, but cross-talk between adjacent electrodes increases
Solution Approach 1:
The resistance variable layer is segmented into multiple layers with different resistance characteristics, which helps isolate electrical signals between adjacent memory elements. This segmentation reduces cross-talk while maintaining relatively simple overall device structure that can be integrated into standard memory arrays.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution achieves stable operation with low electric power consumption, high-density integration, and improved retention characteristics, facilitating further miniaturization and compatibility with semiconductor processes, leading to smaller and thinner electronic devices.
Implementation Method 1
it is required that its resistance value change from a high-resistance value to a low-resistance value or from the low-resistance value to the high-resistance value by applying electric pulses
Implementation Method 2
ion source of the ion source layer 3 forming the storing layer is caused to migrate to the high-resistance layer 2 or the ion source is caused to migrate from the high-resistance layer 2 to the upper electrode 4
Data Source
AI summary
A lower electrode (22) is provided on a semiconductor chip substrate (26). A lower electrode (22) is covered with a first interlayer insulating layer (27) from above. A first contact hole (28) is provided on the lower electrode (22) to penetrate through the first interlayer insulating layer (27). A low-resistance layer (29) forming the resistance variable layer (24) is embedded to fill the first contact hole (28). A high-resistance layer (30) is provided on the first interlayer insulating layer (27) and the low-resistance layer (29). The resistance variable layer (24) is formed by a multi-layer resistance layer including a single layer of the high-resistance layer (30) and a single layer of the low-resistance layer (29). The low-resistance layer (29) forming the memory portion (25) is isolated from at least its adjacent memory portion (25).