Nonvolatile Memory Device With Asymmetric Tunnel Oxide
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Solution Overview
Problem
Flash memory devices are prone to damage during programming due to easy degradation at the interface between the tunnel oxide layer and the semiconductor layer, and require higher voltages during erasing, making them susceptible to damage and reducing their reliability.
Innovation Solution
A nonvolatile memory device with a semiconductor layer having a shallower drain region compared to the source region and a tunnel oxide layer that is thin over the source and drain regions but thicker over the channel region, along with a floating gate and control gate structure, is fabricated using a method involving multiple photoresist patterns and etching processes to reduce damage and optimize voltage application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional flash memory structure with uniform tunnel oxide layer thickness is used, then the device can be fabricated with simpler processes, but the interface between the tunnel oxide layer and semiconductor layer is prone to damage during programming
Solution Approach 1:
The tunnel oxide layer is designed with non-uniform thickness: thinner in source and drain regions to reduce interface damage during programming, and thicker in the channel region to maintain data storage capability. This local variation in thickness optimizes both programming reliability and data retention without requiring completely different fabrication processes.
2Reliability
If a conventional flash memory structure is used, then the fabrication process is simpler, but higher voltage is required during erasing which increases damage susceptibility
Solution Approach 1:
The thinner tunnel oxide layer in source and drain regions reduces the voltage required for charge injection during erasing operations, thereby reducing the overall erasing voltage requirement and minimizing damage susceptibility while maintaining data storage function in the channel region.
3Reliability
If the tunnel oxide layer is made thinner to reduce programming damage, then interface damage is reduced, but data storage capability may be compromised
Solution Approach 1:
The tunnel oxide layer thickness is optimized locally: thinner (50-300 Å) in source and drain regions to reduce programming damage, and thicker in the channel region to maintain data storage capability. This spatial differentiation allows both objectives to be achieved simultaneously.
4Reliability
If a uniform gate insulating layer structure is used, then fabrication is easier, but it cannot optimize both programming and erasing operations
Solution Approach 1:
The gate insulating layer structure varies locally with different thicknesses in different regions, enabling optimization of both programming and erasing operations. The thinner regions facilitate charge injection during programming, while the thicker channel region maintains data storage, achieving dual optimization without fundamentally complicating the fabrication approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces damage during programming and optimizes voltage application, enhancing the reliability and lifespan of the memory device by maintaining efficient electron movement and data storage capabilities.
Implementation Method 1
a tunnel oxide layer which may be thin in regions corresponding to the source and drain regions and thick in a region corresponding to a channel region
Implementation Method 2
the semiconductor layer including a source region which may have an impurity injection region, a drain region which may have a shallower impurity injection region than the impurity injection region of the source region
Data Source
AI summary
A nonvolatile memory device may include a substrate, a semiconductor layer on the substrate, and including a source region, a drain region having a relatively shallower impurity injection region than that of the source region and a channel region disposed between the source and drain regions, a first gate insulating layer on the semiconductor layer, and having regions corresponding to the source and drain regions thinner than a region corresponding to the channel region, and a first gate electrode, a second gate insulating layer, and a second gate electrode which are disposed on the first gate insulating layer. An organic light emitting display device (OLED) may include the nonvolatile memory device.