Nonvolatile Memory Bad Block Voltage Control

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Solution Overview

Problem

Existing nonvolatile memory devices with a multi-plane structure face performance issues when a bad block is present, as simultaneous operations across multiple planes can lead to increased voltage requirements and potential threshold voltage variations, affecting reliability.

Innovation Solution

A nonvolatile memory device and operating method that dynamically adjust operating voltages based on the presence of bad blocks, switching between single and multi-operation modes to optimize performance and reliability by using a control unit to generate appropriate control signals for the address decoder, voltage generator, and page buffer circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multi-operation mode is used to improve performance, then productivity increases, but reliability deteriorates when bad blocks are present due to voltage variations

Engineering Contradiction:
Improvememory operation throughputVSAvoidthreshold voltage consistency
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system dynamically switches between multi-operation mode (for high performance when no bad blocks present) and single-operation mode (for reliability when bad blocks detected). The control unit monitors bad block status and adjusts the operation mode accordingly, making the system adaptive to different operational conditions rather than fixed in one mode.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the operational parameters (voltage levels, operation timing) based on the presence of bad blocks. When bad blocks are detected, the system modifies voltage application patterns to prevent threshold voltage variations, thereby maintaining reliability while still utilizing multi-plane architecture.

Inventive Principle:
Principle #35Parameter changes

2Speed

If simultaneous operations on multiple planes are performed, then speed increases, but device complexity increases due to voltage management requirements

Engineering Contradiction:
Improvememory access speedVSAvoidvoltage control complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The control unit acts as an intermediary that manages the complexity of voltage control for multi-plane operations. It coordinates voltage generation and timing across multiple planes, abstracting the complexity from the rest of the system while enabling fast simultaneous operations when conditions permit.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If operating voltage is increased to maintain performance with bad blocks, then productivity is maintained, but threshold voltage consistency deteriorates

Engineering Contradiction:
Improvememory operation throughputVSAvoidthreshold voltage consistency
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The system dynamically adjusts voltage levels based on operational context. When operating in single-operation mode due to bad blocks, it uses optimized voltage patterns that maintain productivity while ensuring threshold voltage consistency. When in multi-operation mode with no bad blocks, it can use higher voltages for maximum performance.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11462271B2Nonvolatile memory device and operation method thereof
Publication Date: 2022.10.04 SAMSUNG ELECTRONICS CO LTD
  • US11462271B2 patent drawing
  • US11462271B2 patent drawing
  • US11462271B2 patent drawing

AI summary

A nonvolatile memory device and an operating method are provided. The nonvolatile memory device includes a memory cell array including a plurality of planes, each plane including a plurality of memory blocks, an address decoder connected to the memory cell array, a voltage generator configured to apply an operating voltage to the address decoder, a page buffer circuit including page buffers corresponding to each of the planes, a data input/output circuit connected to the page buffer circuit configured to input and output data and a control unit configured to control the operation of the address decoder, the voltage generator, the page buffer circuit, and the data input/output circuit, wherein the control unit is configured to operate in a multi-operation or a single operation by checking whether a memory block of an access address is a bad block.