Nonvolatile Memory Banks with Independent Control Modes
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Solution Overview
Problem
Existing semiconductor memory devices lack the ability to efficiently manage different operational modes and requests from hosts, leading to suboptimal performance in terms of speed, power consumption, and reliability, as they are not effectively divided into separate areas for distinct control.
Innovation Solution
A nonvolatile memory device with multiple banks operating in different modes, each with its own control circuit and control information, allowing for independent or simultaneous write and read operations based on specific operation settings, and a memory controller that manages these banks to optimize performance according to host requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a memory device operates in a single mode, then the control structure is simple, but the adaptability to different host requests is poor
Solution Approach 1:
The memory device is divided into multiple banks (first bank, second bank, etc.), each capable of operating in different modes (first mode, second mode). The command decoder segments the control logic to handle different commands for different banks independently, allowing the system to adapt to various host requests by selecting appropriate banks and modes without requiring a completely different control structure for each scenario.
Solution Approach 2:
The memory device implements dynamic mode switching where banks can transition between first mode and second mode based on received commands. The control circuits dynamically adjust their operation based on the mode selected, enabling the system to adapt its behavior in real-time according to host requests while maintaining a unified underlying control structure.
2Speed
If banks operate in different modes with different latencies, then the responsiveness to specific host requests is improved, but the synchronization and control complexity increases
Solution Approach 1:
Different banks are assigned different operation modes with different latency characteristics based on the specific requirements of the host request. For example, a first bank may operate in a high-speed mode with higher power consumption for performance-critical operations, while a second bank operates in a low-power mode for less time-sensitive operations. This local differentiation allows optimized response speeds for specific requests without requiring complex synchronization across all banks.
Solution Approach 2:
The system changes operational parameters (mode selection) for different banks based on the host request type. The command decoder interprets commands to determine which banks should operate in which modes, effectively changing the operational parameters of individual banks to match the performance requirements of specific operations, thereby achieving differentiated response speeds without uniform complexity.
3Productivity
If the memory device divides into multiple banks with independent control circuits, then the productivity and parallel operation capability are improved, but the device complexity increases
Solution Approach 1:
Multiple banks share a common command decoder and control logic structure, allowing the same control circuitry to manage multiple banks in different modes simultaneously. The control circuits are designed to be multi-functional, handling both first mode and second mode operations across different banks, which reduces the need for entirely separate control paths for each bank while still enabling parallel operations.
Solution Approach 2:
The patent merges the command decoding functionality into a single shared unit that serves all banks, rather than providing separate decoders for each bank. This consolidation reduces the overall number of control circuits while maintaining the ability to independently control each bank's operation mode, thereby improving productivity without proportionally increasing device complexity.
Data Source
AI summary
A nonvolatile memory device includes a command decoder that receives and decodes a first command and a second command, a first control circuit that generates first control information under control of the command decoder decoding the first command, a second control circuit that generates second control information under control of the command decoder decoding the second command, a first bank that includes a first memory cell which operates based on the first control information, and a second bank that includes a second memory cell which operates based on the second control information. A first time to output data from the first bank in response to the first command is different from a second time to output data from the second bank in response to the second command.